Clustered voltage scaling technique for low-power design

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Clustered voltage scaling technique for low-power design

Full text

Pdf (292 KB)

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 3 - 8

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Kimiyoshi Usami	Toshiba Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, Japan and Stanford University, Stanford, CA
Mark Horowitz	Stanford University, Stanford, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 17, Downloads (12 Months): 136, Citation Count: 89

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/224081.224083 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. Chandrakasan, S. Sherng, and R. Broderson ' Low-Power CMOS Digital Design", IBEE J. Solid-State Circuits. vol.27, No.4 A, pp.473-484, April 1992.
	2	M.pedram and J. Rabaey, "Design Solutions and Challenges foc low Power Systems". ICCAD-94 Tutorial D2, San Jose, CA, November 1994.
	3	R. Iris Bahar, H. Cho, G-HachteL, E. Macii, and F. Samenzi, "An Appliction of ADD- Based Timing Analysis to Comb Combinational LOw Power Re-Synthesis', 1994 Int. Workshop on Low Power design, pp39,44. Napa,, CA, April 1994.
	4	Sachin S. Sapatnekar , Sung-Mo Kang, Design Automation for Timing-Driven Layout Synthesis, Kluwer Academic Publishers, Norwell, MA, 1992
	5	M. Smith, "Beyond Claims of Free Transistors and Abondant Instruction Level Parallelism", Hot Chips III. IEEE, Stanford. CA. Auguat 1991.
	6	M, Pedram and B. Press, "Interconnection Length Estimation for Optimized Standard cell Layouts", ICCAD-89. pp390-393, Nov. 1989.

CITED BY 91

	Rob A. Rutenbar , L. Richard Carley , Roberto Zafalon , Nicola Dragone, Low-power technology mapping for mixed-swing logic, Proceedings of the 2001 international symposium on Low power electronics and design, p.291-294, August 2001, Huntington Beach, California, United States
	Kimiyoshi Usami , Mutsunori Igarashi , Takashi Ishikawa , Masahiro Kanazawa , Masafumi Takahashi , Mototsugu Hamada , Hideho Arakida , Toshihiro Terazawa , Tadahiro Kuroda, Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques, Proceedings of the 35th annual conference on Design automation, p.483-488, June 15-19, 1998, San Francisco, California, United States
	J. Chang , M. Pedram, Energy minimization using multiple supply voltages, Proceedings of the 1996 international symposium on Low power electronics and design, p.157-162, August 12-14, 1996, Monterey, California, United States
	Yumin Zhang , Xiaobo Sharon Hu , Danny Z. Chen, Cell selection from technology libraries for minimizing power, Proceedings of the 2001 conference on Asia South Pacific design automation, p.609-614, January 2001, Yokohama, Japan
	Chingwei Yeh , Yin-Shuin Kang , Shan-Jih Shieh , Jinn-Shyan Wang, Layout techniques supporting the use of dual supply voltages for cell-based designs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.62-67, June 21-25, 1999, New Orleans, Louisiana, United States
	Chunhong Chen , Ankur Srivastava , Majid Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.616-629, October 2001
	Chunhong Chen , Majid Sarrafzadeh, Power reduction by simultaneous voltage scaling and gate sizing, Proceedings of the 2000 conference on Asia South Pacific design automation, p.333-338, January 2000, Yokohama, Japan
	Ali Manzak , Chaitali Chakrabarti, A low power scheduling scheme with resources operating at multiple voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.6-14, 2/1/2002
	Jatuchai Pangjun , Sachin S. Sapatnekar, Clock distribution using multiple voltages, Proceedings of the 1999 international symposium on Low power electronics and design, p.145-150, August 16-17, 1999, San Diego, California, United States
	Monica Donno , Luca Macchiarulo , Alberto Macii , Enrico Macii , Massimo Poncino, Enhanced clustered voltage scaling for low power, Proceedings of the 12th ACM Great Lakes symposium on VLSI, April 18-19, 2002, New York, New York, USA
	Kimiyoshi Usami , Mutsunori Igarashi, Low-power design methodology and applications utilizing dual supply voltages, Proceedings of the 2000 conference on Asia South Pacific design automation, p.123-128, January 2000, Yokohama, Japan
	Dennis Sylvester , Himanshu Kaul, Future performance challenges in nanometer design, Proceedings of the 38th conference on Design automation, p.3-8, June 2001, Las Vegas, Nevada, United States
	Chingwei Yeh , Min-Cheng Chang , Shih-Chieh Chang , Wen-Bone Jone, Gate-level design exploiting dual supply voltages for power-driven applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.68-71, June 21-25, 1999, New Orleans, Louisiana, United States
	L. Richard Carley , Akshay Aggarwal, A completey on-chip voltage regulation technique for low power digital circuits, Proceedings of the 1999 international symposium on Low power electronics and design, p.109-111, August 16-17, 1999, San Diego, California, United States
	Mutsunori Igarashi , Kimiyoshi Usami , Kazutaka Nogami , Fumihiro Minami , Yukio Kawasaki , Takahiro Aoki , Midori Takano , Chiharo Mizuno , Takashi Ishikawa , Masahiro Kanazawa , Shinji Sonoda , Makoto Ichida , Naoyuki Hatanaka, A low-power design method using multiple supply voltages, Proceedings of the 1997 international symposium on Low power electronics and design, p.36-41, August 18-20, 1997, Monterey, California, United States
	A. Iyer , D. Marculescu, Power aware microarchitecture resource scaling, Proceedings of the conference on Design, automation and test in Europe, p.190-196, March 2001, Munich, Germany
	Ruchir Puri , Leon Stok , John Cohn , David Kung , David Pan , Dennis Sylvester , Ashish Srivastava , Sarvesh Kulkarni, Pushing ASIC performance in a power envelope, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	De-Sheng Chen , Majid Sarrafzadeh, An exact algorithm for low power library-specific gate re-sizing, Proceedings of the 33rd annual conference on Design automation, p.783-788, June 03-07, 1996, Las Vegas, Nevada, United States
	Anoop Iyer , Diana Marculescu, Microarchitecture-level power management, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.230-239, June 2002
	Sandeep Dhar , Dragan Maksimović, Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.207-209, July 25-27, 2000, Rapallo, Italy
	Ashok Kumar , Magdy Bayoumi , Mohamed Elgamel, A methodology for low power scheduling with resources operating at multiple voltages, Integration, the VLSI Journal, v.37 n.1, p.29-62, February 2004
	Chingwei Yeh , Yin-Shuin Kang, Cell-based layout techniques supporting gate-level voltage scaling for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.983-986, 12/1/2001
	Mongkol Ekpanyapong , Sung Kyu Lim, Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Chunhong Chen , Majid Sarrafzadeh, Provably good algorithm for low power consumption with dual supply voltages, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.76-79, November 07-11, 1999, San Jose, California, United States
	Jatuchai Pangjun , Sachin S. Sapatnekar, Low-power clock distribution using multiple voltages and reduced swings, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.309-318, June 2002
	Noureddine Chabini , Ismaïl Chabini , El Mostapha Aboulhamid , Yvon Savaria, Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Dirk Grunwald, Micro-architecture design and control speculation for energy reduction, Power aware computing, Kluwer Academic Publishers, Norwell, MA, 2002
	Amitabh Menon , S. K. Nandy , Mahesh Mehendale, Multivoltage scheduling with voltage-partitioned variable storage, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Deming Chen , Jason Cong , Fei Li , Lei He, Low-power technology mapping for FPGA architectures with dual supply voltages, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Fei Li , Yan Lin , Lei He , Jason Cong, Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Alberto Nannarelli , Tomás Lang, Low-Power Divider, IEEE Transactions on Computers, v.48 n.1, p.2-14, January 1999
	Akihito Sakanaka , Seiichirou Fujii , Toshinori Sato, A leakage-energy-reduction technique for highly-associative caches in embedded systems, ACM SIGARCH Computer Architecture News, v.32 n.3, p.50-54, June 2004
	W. Hung , Y. Xie , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , Y. Tsai, Total power optimization through simultaneously multiple-v_DD multiple-v_TH assignment and device sizing with stack forcing, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Sarvesh H. Kulkarni , Dennis Sylvester, High performance level conversion for dual VDD design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.926-936, September 2004
	Ashish Srivastava , Dennis Sylvester, Minimizing total power by simultaneous Vdd/Vth assignment, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Fujio Ishihara , Farhana Sheikh , Borivoje Nikolić, Level conversion for dual-supply systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.185-195, February 2004
	Fujio Ishihara , Farhana Sheikh , Borivoje Nikolić, Level conversion for dual-supply systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Farhana Sheikh , Andreas Kuehlmann , Kurt Keutzer, Minimum-power retiming for dual-supply CMOS circuits, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Ashish Srivastava , Dennis Sylvester , David Blaauw, Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Noureddine Chabini , Wayne Wolf, An approach for reducing dynamic power consumption in synchronous sequential digital designs, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.198-204, January 27-30, 2004, Yokohama, Japan
	Noureddine Chabini , Wayne Wolf, Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.6, p.573-589, June 2004
	Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee , Adit D. Singh, Low-power dual V_th pseudo dual V_dd domino circuits, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	R. Reed Taylor , Herman Schmit, Creating a power-aware structured ASIC, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	R. Reed Taylor , Herman Schmit, Enabling energy efficiency in via-patterned gate array devices, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Deming Chen , Jason Cong, Delay optimal low-power circuit clustering for FPGAs with dual supply voltages, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Sarvesh H. Kulkarni , Dennis Sylvester, Power distribution techniques for dual VDD circuits, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Trevor Mudge, Power: A First-Class Architectural Design Constraint, Computer, v.34 n.4, p.52-58, April 2001
	Gang Qu, What is the limit of energy saving by dynamic voltage scaling?, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Maurice Meijer , José Pineda de Gyvez , Ralph Otten, On-chip digital power supply control for system-on-chip applications, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Mikhail Popovich , Eby G. Friedman , Michael Sotman , Avinoam Kolodny, On-chip power distribution grids with multiple supply voltages for high performance integrated circuits, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Himanshu Kaul , Dennis Sylvester, A novel buffer circuit for energy efficient signaling in dual-VDD systems, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Masanori Hariyama , Tetsuya Aoyama , Michitaka Kameyama, Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages, IEEE Transactions on Computers, v.54 n.6, p.642-650, June 2005
	Srivathsan Krishnamohan , Nihar R. Mahapatra, Increasing the energy efficiency of pipelined circuits via slack redistribution, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Deming Chen , Jason Cong , Junjuan Xu, Optimal module and voltage assignment for low-power, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Bin Liu , Yici Cai , Qiang Zhou , Xianlong Hong, Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Sarvesh H. Kulkarni , Ashish N. Srivastava , Dennis Sylvester, A new algorithm for improved VDD assignment in low power dual VDD systems, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Anoop Iyer , Diana Marculescu, Power efficiency of voltage scaling in multiple clock, multiple voltage cores, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.379-386, November 10-14, 2002, San Jose, California
	B. Lasbouygues , R. Wilson , N. Azemard , P. Maurine, Timing analysis in presence of supply voltage and temperature variations, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Abdulkadir U. Diril , Yuvraj S. Dhillon , Abhijit Chatterjee , Adit D. Singh, Low-power domino circuits using NMOS pull-up on off-critical paths, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Ling Wang , Yingtao Jiang , Henry Selvaraj, Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages, The Journal of Supercomputing, v.35 n.1, p.93-113, January 2006
	Bipul C. Paul , Amit Agarwal , Kaushik Roy, Low-power design techniques for scaled technologies, Integration, the VLSI Journal, v.39 n.2, p.64-89, March 2006
	Mikhail Popovich , Eby G. Friedman, Decoupling capacitors for multi-voltage power distribution systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.3, p.217-228, March 2006
	Deming Chen , Jason Cong , Yiping Fan , Junjuan Xu, Optimality study of resource binding with multi-Vdds, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Mark C. Johnson , Kaushik Roy, Datapath scheduling with multiple supply voltages and level converters, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.3, p.227-248, July 1997
	Harmander S. Deogun , Robert Senger , Dennis Sylvester , Richard Brown , Kevin Nowka, A dual-V_DD boosted pulsed bus technique for low power and low leakage operation, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Kaushal R. Gandhi , Nihar R. Mahapatra, Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Deming Chen , Jason Cong , Junjuan Xu, Optimal simultaneous module and multivoltage assignment for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.362-386, April 2006
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	Ling Wang , Yingtao Jiang , Henry Selvaraj, Scheduling and optimal voltage selection with multiple supply voltages under resource constraints, Integration, the VLSI Journal, v.40 n.2, p.174-182, February, 2007
	Stephen P. Boyd , Seung-Jean Kim , Dinesh D. Patil , Mark A. Horowitz, Digital Circuit Optimization via Geometric Programming, Operations Research, v.53 n.6, p.899-932, November-December 2005
	Wan-Ping Lee , Hung-Yi Liu , Yao-Wen Chang, Voltage island aware floorplanning for power and timing optimization, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	B. Lasbouygues , R. Wilson , N. Azemard , P. Maurine, Temperature and voltage aware timing analysis: application to voltage drops, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Jun Cheng Chi , Hung Hsie Lee , Sung Han Tsai , Mely Chen Chi, Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.6, p.637-648, June 2007
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Huaizhi Wu , Martin D.F. Wong , Wilsin Gosti, Postplacement voltage assignment under performance constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.3, p.1-20, July 2008
	A. Sathanur , A. Pullini , L. Benini , A. Macii , E. Macii , M. Poncino, A scalable algorithmic framework for row-based power-gating, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Yu-Cheng Lin , Hsin-Hsiung Huang , Cheng-Chiang Lin , Tsai-Ming Hsieh, Optimal voltage assignment approach for low power using ILP, WSEAS Transactions on Circuits and Systems, v.7 n.7, p.728-737, July 2008
	Hung-Yi Liu , Wan-Ping Lee , Yao-Wen Chang, A provably good approximation algorithm for power optimization using multiple supply voltages, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Wan-Ping Lee , Hung-Yi Liu , Yao-Wen Chang, An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Seiichiri Fujii , Akihito Sakanaka , Akihiro Chiyonobu , Toshinori Sato, A leakage-energy-reduction technique for cache memories in embedded processors, Journal of Embedded Computing, v.2 n.1, p.49-55, January 2006
	Rajarshi Mukherjee , Song Liu , Seda Ogrenci Memik , Somsubhra Mondal, A high-level clustering algorithm targeting dual V_dd FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-20, September 2008
	Mikhail Popovich , Eby G. Friedman , Michael Sotman , Avinoam Kolodny, On-chip power distribution grids with multiple supply voltages for high-performance integrated circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.908-921, July 2008
	Qiang Ma , Evangeline F. Y. Young, Network flow-based power optimization under timing constraints in MSV-driven floorplanning, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Kevin Brownell , Gu-Yeon Wei , David Brooks, Evaluation of voltage interpolation to address process variations, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Liangpeng Guo , Yici Cai , Qiang Zhou , Xianlong Hong, Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.8, p.2084-2090, August 2008
	Wan-Ping Lee , Diana Marculescu , Yao-Wen Chang, Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
	Yu-Cheng Lin , Cheng-Chiang Lin , Hsin-Hsiung Huang , Tsai-Ming Hsieh, Optimal dual voltage assignment algorithm for low power under timing-constraints, Proceedings of the 12th WSEAS international conference on Circuits, p.202-205, July 22-24, 2008, Heraklion, Greece
	Prateek Mishra , Anish Muttreja , Niraj K. Jha, Low-power FinFET circuit synthesis using multiple supply and threshold voltages, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.5 n.2, p.1-23, July 2009
	Keivan Navi , Mehrdad Maeen , Vahid Foroutan , Somayeh Timarchi , Omid Kavehei, A novel low-power full-adder cell for low voltage, Integration, the VLSI Journal, v.42 n.4, p.457-467, September, 2009
	Huaizhi Wu , Martin D. F. Wong, Incremental improvement of voltage assignment, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.2, p.217-230, February 2009
	Wan-Ping Lee , Hung-Yi Liu , Yao-Wen Chang, Voltage-Island partitioning and floorplanning under timing constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.5, p.690-702, May 2009