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A comparison of full and partial predicated execution support for ILP processors
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Source International Symposium on Computer Architecture archive
Proceedings of the 22nd annual international symposium on Computer architecture table of contents
S. Margherita Ligure, Italy
Pages: 138 - 150  
Year of Publication: 1995
ISBN:0-89791-698-0
Also published in ...
Authors
Scott A. Mahlke  Hewlett Packard Laboratories, Palo Alto, CA and Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL
Richard E. Hank  Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL
James E. McCormick  Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL
David I. August  Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL
Wen-Mei W. Hwu  Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 42,   Citation Count: 24
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ABSTRACT

One can effectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential benefits of predicated execution are high, the tradeoffs involved in the design of an instruction set to support predicated execution can be difficult. On one end of the design spectrum, architectural support for full predicated execution requires increasing the number of source operands for all instructions. Full predicate support provides for the most flexibility and the largest potential performance improvements. On the other end, partial predicated execution support, such as conditional moves, requires very little change to existing architectures. This paper presents a preliminary study to qualitatively and quantitatively address the benefit of full and partial predicated execution support. With our current compiler technology, we show that the compiler can use both partial and full predication to achieve speedup in large control-intensive programs. Some details of the code generation techniques are shown to provide insight into the benefit of going from partial to full predication. Preliminary experimental results are very encouraging: partial predication provides an average of 33% performance improvement for an 8-issue processor with no predicate support while full predication provides an additional 30% improvement.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. Lee and A. J. Smith, "Branch prediction strategies and branch target buffer design," IEEE Computer, pp. 6-22, January 1984.
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J. C. Park and M. S. Schlansker, "On predicated execution," Tech. Rep. HPL-91-58, Hewlett Packard Laboratories, Palo Alto, CA, May 1991.
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V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL playdoh architecture specification: Version 1.0," Tech. Rep. HPL- 93-80, Hewlett-Packard Laboratories, Palo Alto, CA 94303, February 1994.
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Hewlett-Packard Company, Cupertino, CA, PA-RISC 1.1 Architecture and Instruction Set Reference Manual, 1990.
 
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D. S. Blickstein et al., "The GEM optimizing compiler system," Digital Technical Journal, vol. 4, pp. 121-136, 1992.
 
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CITED BY  24

Collaborative Colleagues:
Scott A. Mahlke: colleagues
Richard E. Hank: colleagues
James E. McCormick: colleagues
David I. August: colleagues
Wen-Mei W. Hwu: colleagues