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Efficient strategies for software-only protocols in shared-memory multiprocessors
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Source International Symposium on Computer Architecture archive
Proceedings of the 22nd annual international symposium on Computer architecture table of contents
S. Margherita Ligure, Italy
Pages: 38 - 47  
Year of Publication: 1995
ISBN:0-89791-698-0
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Authors
Håkan Grahn  Department of Computer Engineering, Lund University, P.O. Box 118, S-221 00 LUND, Sweden
Per Stenström  Department of Computer Engineering, Lund University, P.O. Box 118, S-221 00 LUND, Sweden
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 14,   Citation Count: 7
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ABSTRACT

The cost, complexity, and inflexibility of hardware-based directory protocols motivate us to study the performance implications of protocols that emulate directory management using software handlers executed on the compute processors. An important performance limitation of such software-only protocols is that software latency associated with directory management ends up on the critical memory access path for read miss transactions. We propose five strategies that support efficient data transfers in hardware whereas directory management is handled at a slower pace in the background by software handlers. Simulations show that this approach can remove the directory-management latency from the memory access path. Whereas the directory is managed in software, the hardware mechanisms must access the memory state in order to enable data transfers at a high speed. Overall, our strategies reach between 60% and 86% of the hardware-based protocol performance.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A. Agarwal, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, K. Kurihara, B-H. Lim, G. Maa, and D. Nussbaum, "The MIT Alewife machine: A large-scale distributed-memory multiprocessor", in: M. Dubois and S.S. Thakkar, eds., Scalable Shared Memory Multiprocessors (Kluwer Academic Publishers, Boston, MA 1990) 240-261
 
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M. Brorsson, E Dahlgren, H. Ndsson, and P. Stenstrtim, "The CacheMire Test Bench- A Flexible and Effective Approach for Simulation of Multlprocessors", In Proceedings c!f the 26th Annual Simulation Symposium, pages 41-49, March 1993.
 
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L.M. Censier and P. Feautner, "A New Solution to Coherence Problems in Multicache Systems", IEEE Transaction on Computers, C- 27(12):II12-1118, December 1978
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Collaborative Colleagues:
Håkan Grahn: colleagues
Per Stenström: colleagues