| Analysis and implementation of hybrid switching |
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International Symposium on Computer Architecture
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Proceedings of the 22nd annual international symposium on Computer architecture
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S. Margherita Ligure, Italy
Pages: 211 - 219
Year of Publication: 1995
ISBN:0-89791-698-0
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Authors
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Kang G. Shin
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Real-Time Computing Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
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Stuart W. Daniel
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Real-Time Computing Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
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Downloads (6 Weeks): 11, Downloads (12 Months): 21, Citation Count: 4
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ABSTRACT
The switching scheme of a point-to-point network determines how packets flow through each node, and is a primary element in determining the network's performance. In this paper, we present and evaluate a new switching scheme called hybrid switching. Hybrid switching dynamically combines both virtual cut-through and wormhole switching to provide higher achievable throughput than wormhole alone, while significantly reducing the buffer space required at intermediate nodes when compared to virtual cut-through. This scheme is motivated by a comparison of virtual cut-through and wormhole switching through cycle-level simulations, and then evaluated using the same methods. To show the feasibility of hybrid switching, as well as to provide a common base for simulating and implementing a variety of switching schemes, we have designed SPIDER, a communication adapter built around a custom ASIC, the Programmable Routing Controller (PRC).
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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W. J. Dally and C. L. Seitz, "The torus routing chip," Journal of Distmbuted Computing, vol. 1, no. 3, pp. 187-196, 1986.
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2
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P. Kermani and L. Kleinrock, "Virtual cutthrough: A new computer communication switching technique," Computer Networks, vol. 3, pp. 267-286, September 1979.
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4
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5
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J. Dolter, S. Daniel, A. Mehra, J. Rexford, W. Feng, and K. Shin, "SPIDER: Flexible and efficient communication support for point-to-point distributed systems," in Proc. Int'l Conf. on Distributed Computing Syslems, pp. 574-580, June 1994.
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6
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7
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Shekhar Borkar , Robert Cohn , George Cox , Thomas Gross , H. T. Kung , Monica Lam , Margie Levine , Brian Moore , Wire Moore , Craig Peterson , Jim Susman , Jim Sutton , John Urbanski , Jon Webb, Supporting systolic and memory communication in iWarp, Proceedings of the 17th annual international symposium on Computer Architecture, p.70-81, May 28-31, 1990, Seattle, Washington, United States
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8
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William J. Dally , J. A. Stuart Fiske , John S. Keen , Richard A. Lethin , Michael D. Noakes , Peter R. Nuth , Roy E. Davison , Gregory A. Fyler, The Message-Driven Processor: A Multicomputer Processing Node with Efficient Mechanisms, IEEE Micro, v.12 n.2, p.23-39, March 1992
[doi> 10.1109/40.127581]
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9
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D. Smitley, F. Hady, and D. Burns, "Hnet: A highperformance network evaluation testbed," Tech. Rep. SRC-TR-91-049, Supercomputing Research Center, Institute for Defense Analyses, December 1991.
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10
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Craig B. Stunkel , Dennis G. Shea , Bülent Abali , Monty Denneau , Peter H. Hochschild , Douglas Joseph , Ben J. Nathanson , Mickey Tsao , Philip R. Varker, Architecture and Implementation of Vulcan, Proceedings of the 8th International Symposium on Parallel Processing, p.268-274, April 01, 1994
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11
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12
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Kevin Bolding , Sen-Ching Cheung , Sung-Eun Choi , Carl Ebeling , Soha Hassoun , Ton Anh Ngo , Robert Wille, The chaos router chip: design and implementation of an adaptive router, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, p.311-320, September 07-10, 1993
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13
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14
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A. Kovaleski, S. Ratheal, and F. Lombardi, "An architecture and interconnection scheme for timesliced buses in real-time processing," Proc. Real- Time Systems Symposium, pp. 20-27, 1986.
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15
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Advanced Micro Devices, 901 Thompson Place, P.O. Box 3453, Sunnyvale CA 94088-3453, Am79168/Am79169 TAXItm-275 Technical Manual, ban-0.1m-1/93/0 17490a ed.
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16
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17
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18
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A. A. Chien, "A cost and speed model for k-ary n-cube wormhole routers," in Proc. Hot Interconnects, August 1993.
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