S-connect: from networks of workstations to supercomputer performance

ABSTRACT

S-Connect is a new high speed, scalable interconnect system that has been developed to support networks of workstations to efficiently share computing resources. It uses off-the-shelf CMOS technology to directly drive fiber-optic systems at speeds greater than 1 Gbit/sec and can realize bisection bandwidths comparable to high-end MPP systems while being >10x more cost-effective. S-Connect systems do not rely on centralized switches, but rather are composed of adaptive, topology independent routing elements that are integrated into each node. The S-Connect routing algorithm is optimized for fine grained, irregular traffic and is designed to support high traffic loads, that can utilize most of the physically available bandwidth. Such traffic is typical of a distributed shared memory system, which is one of the intended applications. S-Connect innovations include a novel distributed phase locking method that allows global synchronization, HW support for multiple message priorities, in-band monitoring and control facilities, and a low overhead channel protocol that supports multiple in-transit messages on the same fiber.The first version of the S-Connect switching element has been successfully implemented in a commercial, 0.65 µm CMOS process.

REFERENCES

• 1: The First Networks of Workstations Workshop, October 1994, San jose, California.
• 2: Nowatzyk, A., Aybay, G., Browne, M, Kelly, E., Parkin, M., Radke, W., Vishin, S., S3.mp: Current Status and Future Directions, Shared Memory Multiprocessor Workshop, International Symposium on Computer Architecture, Chicago, IL, May 1994.
• 3: Nowatzyk, A., Parkin, M., The S3,mp Interconnect System, Hot Interconnect Symposium, Stanford, CA, August 1993.
• 4: Rambus System Specification, 1993, Rambus Inc., Mountain View, CA
• 5: David V. James , Anthony T. Laundrie , Stein Gjessing , Gurindar Sohi, Scalable coherent interface, Computer, v.23 n.6, p.74-77, June 1990 [doi>10.1109/2.55503]
• 6: Futurebus+, P896.2: Physical Layer and Profile Specification, June 1991, IEEE Computer Society
• 7: Stevens, K.S., The Communication Framework for a Distributed Ensemble Architecture, AI Technical Report 47, SRI, Febmary 1986
• 8: William James Dally, A VLSI architecture for concurrent data structures, California Institute of Technology, Pasadena, CA, 1986
• 9: J. H. Kim , Z. Liu , A. A. Chien, Compressionless routing: a framework for adaptive and fault-tolerant routing, Proceedings of the 21ST annual international symposium on Computer architecture, p.289-300, April 18-21, 1994, Chicago, Illinois, United States
• 10: Kermani, P., Kleinrock, L., Virtual Cut-Through: A New Computer Communication Switching Technique, Computer Networks, 3:267-286, 1979.
• 11: Daniel Edward Lenoski, The design and analysis of DASH: a scalable directory-based multiprocessor, Stanford University, Stanford, CA, 1992
• 12: Anant Agarwal , John Kubiatowicz , David Kranz , Beng-Hong Lim , Donald Yeung , Godfrey D'Souza , Mike Parkin, Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors, IEEE Micro, v.13 n.3, p.48-61, May 1993 [doi>10.1109/40.216748]
• 13: Andreas Georg Nowatzyk , Roberto Bisiani, A communication architecture for multiprocessor networks, 1989
• 14: Myrinet Product Information, Myricom Inc, Arcadia, California.
• 15: Gucnter, K. D., Prevention of Deadlocks in Packet-Switched Data Transport Systems, IEEE Transactions on Communica- C-29 (4):512, April 1981

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.1 Network Architecture and Design
          Subjects: Distributed networks
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.1 Large and Medium ("Mainframe") Computers
          Subjects: Super (very large) computers

General Terms:
Algorithms, Design, Performance