Hierarchical optimization of asynchronous circuits

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Hierarchical optimization of asynchronous circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 712 - 717

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Bill Lin	IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Gjalt de Jong	IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Tilman Kolks	IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 4, Citation Count: 0

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Peter A. Beerel , Teresa H.-Y. Meng, Automatic gate-level synthesis of speed-independent circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.581-586, November 1992, Santa Clara, California, United States
	3	E. Brunvand and R.E Sproull. Translating Concurrent Programs into Delay- Insensitive Circuits. In Proc. Int. Conf. on CAD, Nov. 1989.
	4	T. Chu, SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS, Massachusetts Institute of Technology, Cambridge, MA, 1987
	5	Gjalt G. de Jong , Bill Lin, A communicating Petri net model for the design of concurrent asynchronous modules, Proceedings of the 31st annual conference on Design automation, p.49-55, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196272]
	6	David L. Dill, Trace theory for automatic hierarchical verification of speed-independent circuits, MIT Press, Cambridge, MA, 1989
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	8	G. Gopalakrishnan, E. Brunvand, N. Michell and S.M. Nowick. A Correctness Criterion for Asynchronous Circuit Validation and Optimization. In IEEE Trans. of CAD, 13(11):1309-1318,Nov. 1994.
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	10	Alex Kondratyev , Michael Kishinevsky , Bill Lin , Peter Vanbekbergen , Alex Yakovlev, Basic gate implementation of speed-independent circuits, Proceedings of the 31st annual conference on Design automation, p.56-62, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196275]
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	12	B. Lin , G. de Jong , T. Kolks, Modeling and optimization of hierarchical synchronous circuits, Proceedings of the 1995 European conference on Design and Test, p.144, March 06-09, 1995
	13	Alain J. Martin, Programming in VLSI: from communicating processes to delay-insensitive circuits, Developments in concurrency and communication, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1991
	14	D.E. Muller. Lecture Notes on Asynchronous Circuits Theory. Urbana: Univ. of Illinois, 1961.
	15	Chris J. Myers , Teresa H. Y. Meng, Synthesis of Timed Asynchronous Circuits, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.279-284, October 11-14, 1992
	16	M. Rem, J.L.A. van de Snepscheut, and J.T. Udding. Trace Theory and the Definition of Hierarchical Components. In Third Cal-Tech Conference on Very Large Scale Integration, pages 225-239,1983.
	17	Milton Sawasaki , Chantal Ykman-Couvreur , Bill Lin, Externally hazard-free implementations of asynchronous circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.718-724, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217617]
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	20	V.I. Varshavsky, Editor. Self-Timed Control of Concurrent Processes. Kluwer Academic Publishers, 1990.
	21	Peter Vanbekbergen , Bill Lin , Gert Goosens , Hugo De Man, A generalized state assignment theory for transformation on signal transition graphs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.112-117, November 1992, Santa Clara, California, United States
	22	Ch. Ykman-Couvreur, P. Vanbekbergen, and B. Lin. Concurrency Reduction Transformations on State Graphs for Asynchronous Circuit Synthesis. InProc. Int. Workshop on Logic Synthesis, May 1993.
	23	Kenneth Y. Yun , David L. Dill , Steven M. Nowick, Synthesis of 3D Asynchronous State Machines, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.346-350, October 11-14, 1992