ACM Home Page
Please provide us with feedback. Feedback
An algorithm for incremental timing analysis
Full text PdfPdf (135 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents
San Francisco, California, United States
Pages: 696 - 701  
Year of Publication: 1995
ISBN:0-89791-725-1
Authors
Jin-fuw Lee  IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Donald T. Tang  IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 21,   Citation Count: 5
Additional Information:

references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/217474.217613
What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
K. A. Sakallah, T. N. Mudge, and O. A. Olukotun, "Check Tc and min Tc: Timing verification and optimal clocking of synchronous digital circuits," Proc. ICCAD, pp. 552-555, Nov 1990.
 
2
 
3
R.S. Tsay and Ichiang Lin, "A system timing verifier for multiple-phase level-sensitive clock design," Research Report RC 17272, IBM Yorktown, 1991.
 
4
 
5
 
6
 
7
E.L. Lawler, "Combinational Optimization: Networks, and Matroids," Holt, Rinehart and Winston 1976.


Collaborative Colleagues:
Jin-fuw Lee: colleagues
Donald T. Tang: colleagues