Logic clause analysis for delay optimization

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Logic clause analysis for delay optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 668 - 672

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Berhard Rohfleisch	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Bernd Wurth	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Kurt Antreich	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 12

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Circuit structure relations to redundancy and delay," IEEE Transactions on Computer-Aided Design, vol. 13, no. 7, pp. 875-883, 1994.
	3	K. J. Singh, A. R. Wang, R. K. Brayton, and A. Sangiovanni- Vincentelli, "Timing optimization of combinational logic," IEEE/ACM International Conference on Computer-Aided Design, ICCAD, pp. 282-285, 1988.
	4	H. Touati, H. Savoj, and R. K. Brayton, "Delay optimization of combinational logic circuits by clustering and partial collapsing," IEEE/ACM International Conference on Computer- Aided Design, ICCAD, pp. 188-191, 1991.
	5	Alexander Saldanha , Heather Harkness , Patrick C. McGeer , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Performance optimization using exact sensitization, Proceedings of the 31st annual conference on Design automation, p.425-429, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196448]
	6	Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
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	11	D. Bryan, F. Brglez, and R. Lisanke, "Redundancy identification and removal," International Workshop on Logic Synthesis, 1989.
	12	B. Rohfleisch and F. Brglez, "Introduction of permissible bridges with application to logic optimization after technology mapping," The European Design and Test Conference, ED~TC, pp. 87-93, 1994.
	13	Wolfgang Kunz , Prem R. Menon, Multi-level logic optimization by implication analysis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.6-13, November 06-10, 1994, San Jose, California, United States
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	15	Shih-Chieh Chang , Kwang-Ting Cheng , Nam-Sung Woo , Malgorzata Marek-Sadowska, Layout driven logic synthesis for FPGAs, Proceedings of the 31st annual conference on Design automation, p.308-313, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196388]
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CITED BY 12

	Guenter Stenz , Bernhard M. Riess , Bernhard Rohfleisch , Frank M. Johannes, Timing driven placement in interaction with netlist transformations, Proceedings of the 1997 international symposium on Physical design, p.36-41, April 14-16, 1997, Napa Valley, California, United States
	J. A. Espejo , L. Entrena , E. San Millán , E. Oliás, Functional extension of structural logic optimization techniques, Proceedings of the 2001 conference on Asia South Pacific design automation, p.467-472, January 2001, Yokohama, Japan
	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Fast Boolean optimization by rewiring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.262-269, November 10-14, 1996, San Jose, California, United States
	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	Bernhard Rohfleisch , Alfred Kölbl , Bernd Wurth, Reducing power dissipation after technology mapping by structural transformations, Proceedings of the 33rd annual conference on Design automation, p.789-794, June 03-07, 1996, Las Vegas, Nevada, United States
	Paul Tafertshofer , Andreas Ganz , Manfred Henftling, A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.648-655, November 09-13, 1997, San Jose, California, United States
	L. Entrena , E. Olías , J. Uceda , J. Espejo, Timing optimization by an improved redundancy addition and removal technique, Proceedings of the conference on European design automation, p.342-347, September 1996, Geneva, Switzerland
	Paul Tafertshofer , Andreas Ganz, SAT based ATPG using fast justification and propagation in the implication graph, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.139-146, November 07-11, 1999, San Jose, California, United States
	Patrick Vuillod , Luca Benini , Giovanni De Micheli, Generalized matching from theory to application, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.13-20, November 09-13, 1997, San Jose, California, United States
	Hussain Al-Asaad , John P. Hayes, Logic Design Validation via Simulation and Automatic Test Pattern Generation, Journal of Electronic Testing: Theory and Applications, v.16 n.6, p.575-589, Dec. 2000
	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Circuit Optimization by Rewiring, IEEE Transactions on Computers, v.48 n.9, p.962-970, September 1999
	Zhong-Zhen Wu , Shih-Chieh Chang, Multiple wire reconnections based on implication flow graph, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.4, p.939-952, October 2006