Logic synthesis for engineering change

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Logic synthesis for engineering change

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 647 - 652

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Chih-Chang Lin	University of California, Santa Barbara
Kuang-Chien Chen	Fujitsu Laboratories of America, INC.
Shih-Chieh Chang	Synopsys Inc.
Malgorzata Marek-Sadowska	University of California, Santa Barbara
Kwang-Ting Cheng	University of California, Santa Barbara

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 27, Citation Count: 10

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Shih-Chieh Chang , Malgorzata Marek-Sadowska, Perturb and simplify: multi-level boolean network optimizer, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.2-5, November 06-10, 1994, San Jose, California, United States
	4	S. Muroga , Y. Kambayashi , H. C. Lai , J. N. Culliney, The Transduction Method-Design of Logic Networks Based on Permissible Functions, IEEE Transactions on Computers, v.38 n.10, p.1404-1424, October 1989 [doi>10.1109/12.35836]
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	15	Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]
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CITED BY 11

	Raimund Ubar, Design Error Diagnosis with Re-Synthesis in Combinational Circuits, Journal of Electronic Testing: Theory and Applications, v.19 n.1, p.73-82, February 2003
	Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , Juin-Yeu Joseph Lu, Fault-simulation based design error diagnosis for sequential circuits, Proceedings of the 35th annual conference on Design automation, p.632-637, June 15-19, 1998, San Francisco, California, United States
	G. Nam , K. Sakallah , R. Rutenbar, A boolean satisfiability-based incremental rerouting approach with application to FPGAs, Proceedings of the conference on Design, automation and test in Europe, p.560-565, March 2001, Munich, Germany
	Chih-Wei Jim Chang , Malgorzata Marek-Sadowska, ATPG-based logic synthesis: an overview, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.786-789, November 10-14, 2002, San Jose, California
	Sunil P. Khatri , Amit Narayan , Sriram C. Krisnan , Kenneth L. McMillan , Robert K. Brayton , A. Sangiovanni-Vincentelli, Engineering change in a non-deterministic FSM setting, Proceedings of the 33rd annual conference on Design automation, p.451-456, June 03-07, 1996, Las Vegas, Nevada, United States
	Shi-Yu Huang , Kuang-Chien Chen , Kwang-Ting Cheng, Error correction based on verification techniques, Proceedings of the 33rd annual conference on Design automation, p.258-261, June 03-07, 1996, Las Vegas, Nevada, United States
	Andreas Veneris , Jiang Brandon Liu, Incremental Design Debugging in a Logic Synthesis Environment, Journal of Electronic Testing: Theory and Applications, v.21 n.5, p.485-494, October 2005
	Görschwin Fey , Sean Safarpour , Andreas Veneris , Rolf Drechsler, On the relation between simulation-based and SAT-based diagnosis, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	John Moondanos, From Error to Error: Logic Debugging in the Many-Core Era, Electronic Notes in Theoretical Computer Science (ENTCS), v.174 n.4, p.3-7, May, 2007
	Andre Suelflow , Goerschwin Fey , Roderick Bloem , Rolf Drechsler, Using unsatisfiable cores to debug multiple design errors, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Tai-Ying Jiang , Chien-Nan Jimmy Liu , Jing-Yang Jou, Accurate rank ordering of error candidates for efficient HDL design debugging, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.2, p.272-284, February 2009