Extreme delay sensitivity and the worst-case switching activity in VLSI circuits

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Extreme delay sensitivity and the worst-case switching activity in VLSI circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 623 - 627

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Farid N. Najm	ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, IL
Michael Y. Zhang	ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, IL

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 6, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design, pp. 310-323, Feb. 1993.
	2	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	3	Michael G. Xakellis , Farid N. Najm, Statistical estimation of the switching activity in digital circuits, Proceedings of the 31st annual conference on Design automation, p.728-733, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196628]
	4	F. Brglez, P. Powna11, and R. Hum, "Accelerated ATPG and fault grading via testability analysis," IEEE International Symposium on Circuits and Systems, pp. 695-698, June 1985.

CITED BY 13

	Farid N. Najm, Power estimation techniques for integrated circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.492-499, November 05-09, 1995, San Jose, California, United States
	Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru, A practical gate resizing technique considering glitch reduction for low power design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.446-451, June 21-25, 1999, New Orleans, Louisiana, United States
	Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru, A power optimization method considering glitch reduction by gate sizing, Proceedings of the 1998 international symposium on Low power electronics and design, p.221-226, August 10-12, 1998, Monterey, California, United States
	Chin-Chi Teng , Yi-Kan Cheng , Elyse Rosenbaum , Sung-Mo Kang, Hierarchical electromigration reliability diagnosis for VLSI interconnects, Proceedings of the 33rd annual conference on Design automation, p.752-757, June 03-07, 1996, Las Vegas, Nevada, United States
	Ashok K. Murugavel , N. Ranganathan , R. Chandramouli , Srinath Chavali, Least-square estimation of average power in digital CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.55-58, 2/1/2002
	Farid N. Najm, Feedback, correlation, and delay concerns in the power estimation of VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.612-617, June 12-16, 1995, San Francisco, California, United States
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Effects of delay models on peak power estimation of VLSI sequential circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.45-51, November 09-13, 1997, San Jose, California, United States
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, High-level macro-modeling and estimation techniques for switching activity and power consumption, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.538-557, August 2003
	Tan-Li Chou , Kaushik Roy, Power Estimation Under Uncertain Delays, Integrated Computer-Aided Engineering, v.5 n.2, p.107-116, April 1998
	Michael S. Hsiao, Peak power estimation using genetic spot optimization for large VLSI circuits, Proceedings of the conference on Design, automation and test in Europe, p.38-es, January 1999, Munich, Germany
	S. Manich , J. Figueras, Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model, Proceedings of the 1997 European conference on Design and Test, p.597, March 17-20, 1997
	Assim Sagahyroon , Fadi A. Aloul, Using SAT-based techniques in power estimation, Microelectronics Journal, v.38 n.6-7, p.706-715, June, 2007
	Suchismita Roy , P. P. Chakrabarti , Pallab Dasgupta, Satisfiability models for maximum transition power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.8, p.941-951, August 2008