Accurate estimation of combinational circuit activity

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Accurate estimation of combinational circuit activity

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 618 - 622

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Huzefa Mehta	Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA
Manjit Borah	Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA
Robert Michael Owens	Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA
Mary Jane Irwin	Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 11, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. Chandrakasan, T. Sheng , R. W. Brodersen, "Low Power CMOS Digital Design", IEEE J. of Solid-State Circuits, Apr 1992, pp. 473-484.
	2	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	3	B. Kapoor "Improving the accuracy of circuit activity measurement", IWLPD '9~ Workshop Proceedings, pp 111-116.
	4	F. Najm, "Transition Density, A New Measure of Activity in Digital Circuits", IEEE Trans. on Computer Aided Design, Feb 1993, pp. 310-323.
	5	Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin "Accurate Estimation of Combinational Circuit Activity", Tech Report CSE-95-007.
	6	IRSIM USERs Manual.
	7	J. Monteiro, S. Devadas, B. Lin, C-Y Tsui, M. Pedram, "Exact and approximate methods of switching activity estimation in sequential logic circuits", IWfPD '9~ Workshop Proceedings, pp 117-122.
	8	L. Benini, M. Favalli, B. Ricco, "Analysis of hazard contributions to power dissipation in CMOS ICs", IWLPD '9~ Workshop Proceedings, pp 27-32.
	9	M. A. Cirit, "Estimating Dynamic Power Consumption of CMOS Circuits" Proceedings of the Int'l Conference on Computer-Aided Design, Nov 1987, pp 534-537.
	10	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	11	Richard Burch , Farid Najm , Ping Yang , Timothy Trick, McPOWER: a Monte Carlo approach to power estimation, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.90-97, November 1992, Santa Clara, California, United States
	12	R. Murgai, R. Brayton, Alberto Sangiovanni-Vincentelli, "Decomposition of Logic Functions for Minimum Transition Activity", IWLPD '9~ Workshop Proceedings, pp 33-39.
	13	S. M, Kang, "Accurate Simulation of Power Dissipation in VLSI Circuits", IEEE J. of Solid-Slate Circuits, Oct 1986, volume 35, pp 889-891.
	14	Srinivas Devadas, Kurt Keutzer, Jacob White, "Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation", IEEE Trans. on Computer Aided Design, March 1992, pp. 373- 383.

CITED BY 8

	W. Roethig , A. M. Zarkesh , M. Andrews, Power and timing modeling for ASIC designs, Proceedings of the conference on Design, automation and test in Europe, p.969-970, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Jyh-Mou Tseng , Jing-Yang Jou, Two-level logic minimization for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.52-69, Jan. 1999
	Farid N. Najm, Feedback, correlation, and delay concerns in the power estimation of VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.612-617, June 12-16, 1995, San Francisco, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Ki-Seok Chung , Taewhan Kim , C. L. Liu, G-vector: A New Model for Glitch Analysis in Logic Circuits, Journal of VLSI Signal Processing Systems, v.27 n.3, p.235-251, March 1, 2001
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Hyeonmin Lim , Kyungsoo Lee , Youngjin Cho , Naehyuck Chang, Flip-flop insertion with shifted-phase clocks for FPGA power reduction, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.335-342, November 06-10, 2005, San Jose, CA
	Hoon Choi , Seung Ho Hwang, Improving the Accuracy of Support-Set Finding Method for Power Estimation of Combinational Circuits, Proceedings of the 1997 European conference on Design and Test, p.526, March 17-20, 1997