Code optimization techniques for embedded DSP microprocessors

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Code optimization techniques for embedded DSP microprocessors

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 599 - 604

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Stan Liao	MIT Department of EECS, Cambridge, MA
Srinivas Devadas	MIT Department of EECS, Cambridge, MA
Kurt Keutzer	Synopsys, Inc., Mountain View, CA
Steve Tjiang	Synopsys, Inc., Mountain View, CA
Albert Wang	Synopsys, Inc., Mountain View, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 23, Citation Count: 17

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	2	Wei Kai Cheng , Youn Long Lin, Code generation for a DSP processor, Proceedings of the 7th international symposium on High-level synthesis, p.82-87, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	3	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	4	John R. Ellis, Bulldog: a compiler for VLSI architectures, MIT Press, Cambridge, MA, 1986
	5	J.A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Trnsactions on Computers, C- 30(7):478-490, 1981.
	6	Jack G. Ganssle, The Art of Programming Embedded Systems, Academic Press, Inc., Orlando, FL, 1991
	7	Texas Instruments. TMS320C2x User's Guide. Texas Instruments, January 1993. Revision C.
	8	Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang , Albert Wang, Storage assignment to decrease code size, Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation, p.186-195, June 18-21, 1995, La Jolla, California, United States
	9	E Marwedel and G. Goossens, editors. Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995. Proceedings of the 1994 Dagstuhl Workshop on Code Generation for Embedded Processors.
	10	Shlomit S. Pinter, Register allocation with instruction scheduling, Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation, p.248-257, June 21-25, 1993, Albuquerque, New Mexico, United States
	11	V. Zivojnovi6, J. Martfnez Velarde, and C. Schl~iger. DSPstone: A DSP-oriented Benchmarking Methodology. Technical report, Aachen University of Technology, August 1994.

CITED BY 17

	Wei-Kai Cheng , Youn-Long Lin, Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.3, p.231-256, July 1999
	Mahesh Mehendale , G. Venkatesh , S. D. Sherlekar, Optimized code generation of multiplication-free linear transforms, Proceedings of the 33rd annual conference on Design automation, p.41-46, June 03-07, 1996, Las Vegas, Nevada, United States
	Steven Vercauteren , Bill Lin , Hugo De Man, A strategy for real-time kernel support in application-specific HW/SW embedded architectures, Proceedings of the 33rd annual conference on Design automation, p.678-683, June 03-07, 1996, Las Vegas, Nevada, United States
	H. Tomiyama , T. Ishihara , A. Inoue , H. Yasuura, Instruction scheduling for power reduction in processor-based system design, Proceedings of the conference on Design, automation and test in Europe, p.855-860, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Clifford Liem , Pierre Paulin , Ahmed Jerraya, Address calculation for retargetable compilation and exploration of instruction-set architectures, Proceedings of the 33rd annual conference on Design automation, p.597-600, June 03-07, 1996, Las Vegas, Nevada, United States
	Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang , Albert Wang, Storage assignment to decrease code size, ACM SIGPLAN Notices, v.30 n.6, p.186-195, June 1995
	Jens Wagner , Rainer Leupers, C Compiler Design for an Industrial Network Processor, ACM SIGPLAN Notices, v.36 n.8, p.155-164, Aug. 2001
	Heidi Pan , Krste Asanović, Heads and tails: a variable-length instruction format supporting parallel fetch and decode, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
	Catherine H. Gebotys, An efficient model for DSP code generation: performance, code size, estimated energy, Proceedings of the 10th international symposium on System synthesis, p.41-47, September 17-19, 1997, Antwerp, Belgium
	Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang, Instruction selection using binate covering for code size optimization, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang, Instruction selection using binate covering for code size optimization, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.393-399, November 05-09, 1995, San Jose, California, United States
	Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau, On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.682-704, July 2000
	Takeshi Ogasawara , Hideaki Komatsu , Toshio Nakatani, Optimizing precision overhead for x86 processors, Software—Practice & Experience, v.34 n.9, p.875-893, 25 July 2004
	Björn Franke , Michael O'Boyle , John Thomson , Grigori Fursin, Probabilistic source-level optimisation of embedded programs, ACM SIGPLAN Notices, v.40 n.7, July 2005
	Steve Haga , Andrew Webber , Yi Zhang , Nghi Nguyen , Rajeev Barua, Reducing code size in VLIW instruction scheduling, Journal of Embedded Computing, v.1 n.3, p.415-433, August 2005
	F. Agakov , E. Bonilla , J. Cavazos , B. Franke , G. Fursin , M. F. P. O'Boyle , J. Thomson , M. Toussaint , C. K. I. Williams, Using Machine Learning to Focus Iterative Optimization, Proceedings of the International Symposium on Code Generation and Optimization, p.295-305, March 26-29, 2006
	A. E. Doroshenko , D. V. Ragozin, Using Graph Models in Retargetable Optimizing Compilers for Microprocessors with VLIW Architectures, Cybernetics and Systems Analysis, v.39 n.2, p.192-211, March-April 2003