Conflict modelling and instruction scheduling in code generation for in-house DSP cores

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Conflict modelling and instruction scheduling in code generation for in-house DSP cores

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 593 - 598

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Adwin H. Timmer	Eindhoven University of Technology, Department of Electrical Engineering Design Automation Section, P.O. Box 513, 5600 MB Eindhoven, The Netherlands and Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands
Marino T.J. Strik	Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands
Jef L. van Meerbergen	Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands
Jochen A.G. Jess	Eindhoven University of Technology, Department of Electrical Engineering Design Automation Section, P.O. Box 513, 5600 MB Eindhoven, The Netherlands

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 10, Citation Count: 21

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Chou94	Pai Chou , Gaetano Borriello, Software scheduling in the co-synthesis of reactive real-time systems, Proceedings of the 31st annual conference on Design automation, p.1-4, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196247]
	Dulm63	A.L. Dulmage and N.S. Mendelsohn, "Two Algorithms for Bipartite Graphs", J. Soc. Indust. Appl. Math., Vol. 11, No. 1, pp. 183-194, 1963.
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	Praet94	Johan Van Praet , Gert Goossens , Dirk Lanneer , Hugo De Man, Instruction set definition and instruction selection for ASIPs, Proceedings of the 7th international symposium on High-level synthesis, p.11-16, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	Strik95	M. Strik , J. van Meerbergen , A. Timmer , J. Jess , S. Note, Efficient code generation for in-house DSP-cores, Proceedings of the 1995 European conference on Design and Test, p.244, March 06-09, 1995
	Timm93	Adwin H. Timmer , Jochen A. G. Jess, Execution interval analysis under resource constraints, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.454-459, November 07-11, 1993, Santa Clara, California, United States
	Timm95a	A. H. Timmer , J. A. G. Jess, Exact scheduling strategies based on bipartite graph matching, Proceedings of the 1995 European conference on Design and Test, p.42, March 06-09, 1995
	Timm95b	A.H. Timmer, Ph.D. Thesis (to appear in 1995).

CITED BY 21

	Chuck Monahan , Forrest Brewer, Concurrent analysis techniques for data path timing optimization, Proceedings of the 33rd annual conference on Design automation, p.47-50, June 03-07, 1996, Las Vegas, Nevada, United States
	R. Leupers , P. Marwedel, Instruction selection for embedded DSPs with complex instructions, Proceedings of the conference on European design automation, p.200-205, September 1996, Geneva, Switzerland
	Q. Zhao , T. Basten , B. Mesman , C. A. J. van Eijk , J. A. G. Jess, Static resource models of instruction sets, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Rainer Leupers , Peter Marwedel, Time-constrained code compaction for DSPs, Proceedings of the 8th international symposium on System synthesis, p.54-59, September 13-15, 1995, Cannes, France
	Koen Van Eijk , Bart Mesman , Carlos A. Alba Pinto , Qin Zhao , Marco Bekooij , Jef Van Meerbergen , Jochen Jess, Constraint analysis for code generation: basic techniques and applications in FACTS, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.4, p.774-793, Oct. 2000
	Peter Marwedel, Code generation for core processors, Proceedings of the 34th annual conference on Design automation, p.232-237, June 09-13, 1997, Anaheim, California, United States
	B. Mesman , M. Strik , A. H. Timmer , J. L. van Meerbergen , J. A. G. Jess, A constraint driven approach to loop pipelining and register binding, Proceedings of the conference on Design, automation and test in Europe, p.377-383, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Jens Wagner , Rainer Leupers, C Compiler Design for an Industrial Network Processor, ACM SIGPLAN Notices, v.36 n.8, p.155-164, Aug. 2001
	Björn Franke , Michael O'Boyle, An empirical evaluation of high level transformations for embedded processors, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
	Catherine H. Gebotys, An efficient model for DSP code generation: performance, code size, estimated energy, Proceedings of the 10th international symposium on System synthesis, p.41-47, September 17-19, 1997, Antwerp, Belgium
	Bart Mesman , Marino T. J. Strik , Adwin H. Timmer , Jef L. van Meerbergen , Jochen A. G. Jess, Constraint analysis for DSP code generation, Proceedings of the 10th international symposium on System synthesis, p.33-40, September 17-19, 1997, Antwerp, Belgium
	Bart Mesman , Adwin H. Timmer , Jef L. van Meerbergen , Jochen A. G. Jess, Constraint analysis for DSP code generation, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Qin Zhao , Bart Mesman , Twan Basten, Static resource models for code-size efficient embedded processors, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.219-250, May 2003
	Björn Franke , Michael O'boyle, Array recovery and high-level transformations for DSP applications, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.132-162, May 2003
	Carlos Alba-Pinto , Bart Mesman , Jochen Jess, Constraint satisfaction for relative location assignment and scheduling, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Rainer Leupers, Code generation for embedded processors, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Rainer Leupers, Exploiting conditional instructions in code generation for embedded VLIW processors, Proceedings of the conference on Design, automation and test in Europe, p.23-es, January 1999, Munich, Germany
	A. Balboni , W. Fornaciari , D. Sciuto , M. Vincenzi, The use of a virtual instruction set for the software synthesis of Hw/Sw embedded systems, Proceedings of the 9th international symposium on System synthesis, p.77, November 06-08, 1996
	Bart Mesman , Carlos A. Alba Pinto , Koen Van Eijk, Efficient Scheduling of DSP Code on Processors with Distributed Register Files, Proceedings of the 12th international symposium on System synthesis, p.100, November 01-04, 1999
	Marc Quax , Jos Huisken , Jef van Meerbergen, A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver, Proceedings of the conference on Design, automation and test in Europe, p.30230, February 16-20, 2004
	Alastair Murray , Björn Franke, Fast source-level data assignment to dual memory banks, Proceedings of the 11th international workshop on Software & compilers for embedded systems, March 13-14, 2008, Munich, Germany