Effects of FPGA architecture on FPGA routing

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Effects of FPGA architecture on FPGA routing

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 574 - 578

Year of Publication: 1995

ISBN:0-89791-725-1

Author

Stephen Trimberger

Xilinx, Inc., 2100 Logic Drive, San Jose, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	2	Abbas El Gamal , Jonathan Greene , Vwani Roychowdhury, Segmented channel routing in nearly as efficient as channel routing (and just as hard), Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, p.192-211, April 1991
	3	A. E1 Gamal, "Two-Dimensional Stochastic Model for Interconnection in Master Slice Integrated Circuits," IEEE Transactions on Circuits and Systems, vol. CAS-28, no. 2, February 1981.
	4	J. Frankle, Iterative and adaptive slack allocation for performance-driven layout and FPGA routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.536-542, June 08-12, 1992, Anaheim, California, United States
	5	Jonathan Greene , Vwani Roychowdhury , Sinan Kaptanoglu , Abbas El Gamal, Segmented channel routing, Proceedings of the 27th ACM/IEEE conference on Design automation, p.567-572, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123405]
	6	W.R. Heller, et. al., "Prediction of Wiring Space Requirements for LSI," Journal of Design Automation and Fault Tolerant Computing, May 1978.
	7	Paul Penfield, Jr. , Jorge Rubinstein, Signal delay in RC tree networks, Proceedings of the 18th conference on Design automation, p.613-617, June 29-July 01, 1981, Nashville, Tennessee, United States
	8	Stephen M. Trimberger, Field-Programmable Gate Array Technology, Kluwer Academic Publishers, Norwell, MA, 1994
	9	Y. Wu and M. Marek-Sadowska, "Graph Based Analysis of FPGA Routing", Proceedings of Euro-DA C, IEEE, 1993.

CITED BY 2

	Michael J. Alexander, Power optimization for FPGA look-up tables, Proceedings of the 1997 international symposium on Physical design, p.156-162, April 14-16, 1997, Napa Valley, California, United States
	William N. N. Hung , Xiaoyu Song , El Mostapha Aboulhamid , Andrew Kennings , Alan Coppola, Segmented channel routability via satisfiability, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.517-528, October 2004