Orthogonal greedy coupling

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Orthogonal greedy coupling: a new optimization approach to 2-D FPGA routing

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 568 - 573

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Yu-Liang Wu	Cadence Design Systems, Inc. San Jose, CA
Malgorzata Marek-Sadowska	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 6, Citation Count: 9

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. Hsieh, et. al. "Third-Generation Architecture Boosts Speed and Density of Field Programmable Gate Arrays", Proc. CICC, pp. 31.2.1-31.2.7. 1990.
	2	Steven Trimberger , Mon-Ren Chene, Placement-Based Partitioning for Lookup-Table-Based FPGAs, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.91-94, October 11-14, 1992
	3	M. Palczewski, Plane parallel a maze router and its application to FPGAs, Proceedings of the 29th ACM/IEEE conference on Design automation, p.691-697, June 08-12, 1992, Anaheim, California, United States
	4	S. Brown, J. Rose, and Z. G. Vranesic, "A Detailed Router for Field- Programmable Gate Arrays", IEEE Trans. on Computer-Aided Design, Vol. 11, No. 5. pp. 620-628, May 1992.
	5	Guy G. Lemieux and Stephen D. Brown, "A Detailed Routing Algorithm for Allocating Wire Segments in FPGAs", 4th ACM/SIGDA Physical Design Workshop, 1993.
	6	Johnson, Demers, Ullman, Garey and Graham, "Worst-Case Performance Bounds for Simple One-Dimensional Packing Algorithms", SIAM Jr. On Computing, 3(4), pp.299-325 (1974).
	7	Yu-Liang Wu , Malgorzata Marek-Sadowska, On two-dimensional fpga routing: theoretical analysis and novel effective solutions, 1994
	8	Y.L. Wu, S. Tsukiyama, and M. Marek-Sadowska, "Graph Based Analysis of 2-D FPGA Routing", submitted for publication.
	9	Y.L. Wu, and M. Marek-Sadowska, "An Efficient Router for 2-D Field Programmable Gate Arrays", Proc. of EDAC, pp. 412-416, 1994.
	10	Yu-Liang Wu , Douglas Chang, On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.362-366, November 06-10, 1994, San Jose, California, United States
	11	Akihiro Hashimoto , James Stevens, Wire routing by optimizing channel assignment within large apertures, Proceedings of the 8th workshop on Design automation, p.155-169, June 28-30, 1971, Atlantic City, New Jersey, United States [doi>10.1145/800158.805069]
	12	Yachyang Sun , Ting-Chi Wang , C. K. Wong , C. L. Liu, Routing for symmetric FPGAs and FPICs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.486-490, November 07-11, 1993, Santa Clara, California, United States
	13	Yachyang Sun , C. L. Liu, Routing in a new 2-dimensional FPGA/FPIC routing architecture, Proceedings of the 31st annual conference on Design automation, p.171-176, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196327]
	14	T. Ohtsuki at al, "One-Dimensional Logic Gate Assignment and Interval Graphs", IEEE Trans. on Circuits and Systems, Vol. CAS-26, No. 9, pp. 675- 684, 1979.

CITED BY 9

	Guy G. F. Lemieux , Stephen D. Brown , Daniel Vranesic, On two-step routing for FPGAS, Proceedings of the 1997 international symposium on Physical design, p.60-66, April 14-16, 1997, Napa Valley, California, United States
	K. K. Lee , Martin D. F. Wong, LRoute: a delay minimal router for hierarchical CPLDs, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.12-20, February 2001, Monterey, California, United States
	Yao-Wen Chang , Yu-Tsang Chang, An architecture-driven metric for simultaneous placement and global routing for FPGAs, Proceedings of the 37th conference on Design automation, p.567-572, June 05-09, 2000, Los Angeles, California, United States
	Nak Woong Eum , Taewhan Kim , Chong Min Kyung, A router for symmetrical FPGAs based on exact routing density evaluation, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation, IEEE Transactions on Computers, v.53 n.7, p.829-842, July 2004
	Stephen Brown , Muhammad Khellah , Zvonko Vranesic, Minimizing FPGA Interconnect Delays, IEEE Design & Test, v.13 n.4, p.16-23, December 1996
	Jai-Ming Lin , Song-Ra Pan , Yao-Wen Chang, Graph matching-based algorithms for array-based FPGA segmentation design and routing, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	Ian Kuon , Russell Tessier , Jonathan Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends® in Electronic Design Automation, v.2 n.2, p.135-253, February 2008