A performance and routablity driven router for FPGAs considering path delays

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A performance and routablity driven router for FPGAs considering path delays

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 557 - 561

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Yuh-sheng Lee	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.
Allen C.-H. Wu	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 18

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. J. Alexander and G. Robins, "An Architecture- Independent Unified Approach to FPGA Routing," Proc. of A CM/SIGDA Physical Design Workshop, 1994.
	2	S. Brown, J. Rose, and Z. G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays," IEEE Trans. on CAD, Vol. 11, No. 5, pp. 620-628, May 1992.
	3	C.-D. Chen, Y.-S. Lee, A. C.-H. Wu, and Y.-L. Lin, "TRACER-fpga: A Router for RAM-Based FPGA's", IEEE Trans. on CAD, Vol. 14, No. 3, March 1995.
	4	J. Frankle, Iterative and adaptive slack allocation for performance-driven layout and FPGA routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.536-542, June 08-12, 1992, Anaheim, California, United States
	5	R. M. Kling and P. Banerjee, "ESP: Placement by Simulated Evolution," IEEE Trans. on CAD, Vol. 8, pp. 245- 256, March 1989.
	6	E. S. Kuh and M. Marek-Sadowska, "Global Routing," Layout Design and Verification, T. Ohtsuki, editor, North-Holland, 1985.
	7	C. Y. Lee, "An Algorithm for Path Connections and its Applications," IRE Trans. on Electronic Computers, Vol. EC-10, pp. 346-365, Sept. 1961.
	8	G. G. Lemieux and S. D. Brown, "A Detailed Routing Algorithm for Allocating Wire Segments in Field- Programmable Gate ARRAYS," Proc. of ACM/SIGDA Physical Design Workshop, pp. 215-226, 1993.
	9	F. D. Lewis , Wang Chia-Chi Pong, A negative reinforcement method for PGA routing, Proceedings of the 30th international conference on Design automation, p.601-605, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165064]
	10	Y.-L. Lin, Y.-C. Hsu, and F.-S. Tsai, "SILK: A Simulated Evolution Router," IEEE Trans. on CAD, Vol. 8, No. 10, pp. 1108-1114, Oct. 1989.
	11	Paul Penfield, Jr. , Jorge Rubinstein, Signal delay in RC tree networks, Proceedings of the 18th conference on Design automation, p.613-617, June 29-July 01, 1981, Nashville, Tennessee, United States
	12	J. Rose and S. Brown, "Flexibility of Interconnection Structures for Field-Programmable Gate Arrays," IEEE J. of Solid-State Circuits, Vol. 26, No. 3, pp. 277-282, 1991.
	13	Y.-L. Wu and M. Marek-Sadowska, "Graph Based Analysis of FPGA Routing," Proc. of Euro-DAC, pp. 104- 109, 1994.

CITED BY 18

	Gi-Joon Nam , Fadi Aloul , Karem Sakallah , Rob Rutenbar, A comparative study of two Boolean formulations of FPGA detailed routing constraints, Proceedings of the 2001 international symposium on Physical design, p.222-227, April 01-04, 2001, Sonoma, California, United States
	Yao-Wen Chang , Kai Zhu , D. F. Wong, Timing-driven routing for symmetrical array-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.433-450, July 2000
	Hongbing Fan , Jiping Liu , Yu-Liang Wu , Chak-Chung Cheung, On optimum switch box designs for 2-D FPGAs, Proceedings of the 38th conference on Design automation, p.203-208, June 2001, Las Vegas, Nevada, United States
	Seokjin Lee , D. F. Wong, Timing-driven routing for FPGAs based on Lagrangian relaxation, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Yao-Wen Chang , Yu-Tsang Chang, An architecture-driven metric for simultaneous placement and global routing for FPGAs, Proceedings of the 37th conference on Design automation, p.567-572, June 05-09, 2000, Los Angeles, California, United States
	Guy G. F. Lemieux , Stephen D. Brown , Daniel Vranesic, On two-step routing for FPGAS, Proceedings of the 1997 international symposium on Physical design, p.60-66, April 14-16, 1997, Napa Valley, California, United States
	Hongbing Fan , Jiping Liu , Yu Liang Wu, General models for optimum arbitrary-dimension FPGA switch box designs, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Guang-Ming Wu , Jai-Ming Lin , Yao-Wen Chang, Performance-driven placement for dynamically reconfigurable FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.628-642, October 2002
	Seokjin Lee , Hua Xiang , D. F. Wong , Richard Y. Sun, Wire type assignment for FPGA routing, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Gi-Joon Nam , Fadi Aloul , Karem A. Sakallah , Rob A. Rutenbar, A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints, IEEE Transactions on Computers, v.53 n.6, p.688-696, June 2004
	Hongbing Fan , Jiping Liu , Yu-Liang Wu, General Models and a Reduction Design Technique for FPGA Switch Box Designs, IEEE Transactions on Computers, v.52 n.1, p.21-30, January 2003
	Stephen Brown , Muhammad Khellah , Zvonko Vranesic, Minimizing FPGA Interconnect Delays, IEEE Design & Test, v.13 n.4, p.16-23, December 1996
	Jiping Liu , Hongbing Fan , Yu-Liang Wu, On improving FPGA routability applying multi-level switch boxes, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Jai-Ming Lin , Song-Ra Pan , Yao-Wen Chang, Graph matching-based algorithms for array-based FPGA segmentation design and routing, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	R. Fung , V. Betz , W. Chow, Simultaneous short-path and long-path timing optimization for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.838-845, November 07-11, 2004
	Seokjin Lee , Yongseok Cheon , Martin D. F. Wong, A Min-Cost Flow Based Detailed Router for FPGAs, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.388, November 09-13, 2003
	Keith So, Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA