On optimal board-level routing for FPGA-based logic emulation

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On optimal board-level routing for FPGA-based logic emulation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 552 - 556

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Wai-Kei Mak	Department of Computer Sciences, University of Texas at Austin
D. F. Wong	Department of Computer Sciences, University of Texas at Austin

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 4, Citation Count: 6

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	2	Stephen M. Trimberger, Field-Programmable Gate Array Technology, Kluwer Academic Publishers, Norwell, MA, 1994
	3	J. Varghese, M. Butts, and J. Baatcheller, "An Efficient Logic Emulation System", IEEE Transactions on VLSL VoI. 1, No. 2, June 1993, 171-174.
	4	M. Slimane-Kadi, D. Brasen, and G. Saucier, "A Fast- FPGA Prototyping System that Uses Inexpensive High- Performance FPIC," A CM/SIGDA International Workshop on Field-Programmable Gate Arrays, Feb 1994.
	5	L. Maliniak, "Multiplexing Enhances Hardware Emulation," Electronic Design, Nov. 1992, 76-78,
	6	Stephen Walters, Computer-Aided Prototyping for ASIC-Based Systems, IEEE Design & Test, v.8 n.2, p.4-10, April 1991 [doi>10.1109/54.82034]
	7	K. Yamada, H. Nakada, A. Tsutsui, and N. Ohta, "High- Speed Emulation of Communication Circuits on a Multiple- FPGA System," A CM/SIGDA International Workshop on Field-Programmable Gate Arrays, Feb 1994.
	8	Nan-Chi Chou , Lung-Tien Liu , Chung-Kuan Cheng , Wei-Jin Dai , Rodney Lindelof, Circuit partitioning for huge logic emulation systems, Proceedings of the 31st annual conference on Design automation, p.244-249, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196365]
	9	H.H. Yang, and D. F. Wong, "Area/Pin-Constrained Circuit Clustering for Delay Minimization," A CM/SIGDA International Workshop on Field-Programmable Gate Arrays, Feb 1994.
	10	C. Berge, The Theory of Graphs and Its Applications, John Wiley and Sons, 1962.
	11	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	12	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	13	W.K. Mak, and D.F. Wong, On Optimal Board-Level Routing for FPGA-based Logic Emulation, Technical Report, TR94-30, Department of Computer Sciences, University of Texas at Austin, 1994.

CITED BY 6

	Wai-Kei Mak , D. F. Wong, Board-level multi-terminal net routing for FPGA-based logic emulation, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.339-344, November 05-09, 1995, San Jose, California, United States
	Ranga Vemuri , Sriram Govindarajan , Iyad Ouaiss , Meenakshi Kaul , Vinoo Srinivasan , Shankar Radhakrishnan , Sujatha Sundaraman , Satish Ganesan , Awartika Pandey , Preetham Lakshmikanthan, Automated design synthesis and partitioning for adaptive reconfigurable hardware, Hardware implementation of intelligent systems, Physica-Verlag GmbH, Heidelberg, Germany, 2001
	Chau-Shen Chen , TingTing Hwang , C. L. Liu, Architecture driven circuit partitioning, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.408-411, November 08-12, 1998, San Jose, California, United States
	Abdel Ejnioui , N. Ranganathan, Multi-terminal net routing for partial crossbar-based multi-FPGA systems, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.176-185, February 21-23, 1999, Monterey, California, United States
	Wai-Kei Mak , D. F. Wong, Board-level multiterminal net routing for FPGA-based logic emulation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.151-167, April 1997
	Abdel Ejnioui , Nagarajan Ranganathan, Multiterminal net routing for partial crossbar-based multi-FPGA systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.71-78, February 2003