Residue BDD and its application to the verification of arithmetic circuits

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Residue BDD and its application to the verification of arithmetic circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 542 - 545

Year of Publication: 1995

ISBN:0-89791-725-1

Author

Shinji Kimura

Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-01, JAPAN

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 8, Citation Count: 5

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	2	S. Minato, N. Ishiura, and S. Yajima, "Fast Tautology Checking Using Shared Binary Decision Diagram -Benchmark Results-", in Proc. IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, Nov. 1989, pp. 580-584.
	3	Randal E. Bryant, Symbolic Boolean manipulation with ordered binary-decision diagrams, ACM Computing Surveys (CSUR), v.24 n.3, p.293-318, Sept. 1992 [doi>10.1145/136035.136043]
	4	Jerry R. Burch, Using BDDs to verify multipliers, Proceedings of the 28th conference on ACM/IEEE design automation, p.408-412, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127703]
	5	J. Jain, J. Bitner, J. A. Abraham, and D. S. Fussell, "Functional Partitioning for Verification and Related Problems", in Proc. of the 1992 Brown/MIT Conference, 1992, pp. 210-226.
	6	Randy E. Bryant , Yirng Chen, Verification of Arithmetic Functions with Binary Moment Diagrams, Carnegie Mellon University, Pittsburgh, PA, 1994
	7	Norman R. Scott, Computer number systems and arithmetic, Prentice-Hall, Inc., Upper Saddle River, NJ, 1984

CITED BY 5

	Ying-Tsai Chang , Kwang Ting, Self-referential verification of gate-level implementations of arithmetic circuits, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Tony Stornetta , Forrest Brewer, Implementation of an efficient parallel BDD package, Proceedings of the 33rd annual conference on Design automation, p.641-644, June 03-07, 1996, Las Vegas, Nevada, United States
	Kiyoharu Hamaguchi , Akihito Morita , Shuzo Yajima, Efficient construction of binary moment diagrams for verifying arithmetic circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.78-82, November 05-09, 1995, San Jose, California, United States
	Edmund M. Clarke , Bernd-Holger Schlingloff, Model checking, Handbook of automated reasoning, Elsevier Science Publishers B. V., Amsterdam, The Netherlands, 2001
	Katarzyna Radecka , Zeljko Zilic, Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.128-131, November 10-14, 2002, San Jose, California