On the bounded-skew clock and Steiner routing problems

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On the bounded-skew clock and Steiner routing problems

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 508 - 513

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Dennis J. H. Huang	UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng	UCLA Computer Science Dept., Los Angeles, CA
Chung-Wen Albert Tsao	UCLA Computer Science Dept., Los Angeles, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 20, Citation Count: 29

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	15	Samir Khuller , Balaji Raghavachari , Neal Young, Balancing minimum spanning and shortest path trees, Proceedings of the fourth annual ACM-SIAM Symposium on Discrete algorithms, p.243-250, January 25-27, 1993, Austin, Texas, United States
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CITED BY 29

	M. Saitoh , M. Azuma , A. Takahashi, Clustering based fast clock scheduling for light clock-tree, Proceedings of the conference on Design, automation and test in Europe, p.240-245, March 2001, Munich, Germany
	Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.341-388, July 1998
	Tianxiong Xue , Ernest S. Kuh, Post routing performance optimization via multi-link insertion and non-uniform wiresizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.575-580, November 05-09, 1995, San Jose, California, United States
	C. Albrecht , B. Korte , J. Schietke , J. Vygen, Cycle time and slack optimization for VLSI-chips, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.232-238, November 07-11, 1999, San Jose, California, United States
	Atsushi Takahashi , Kazunori Inoue , Yoji Kajitani, Clock-tree routing realizing a clock-schedule for semi-synchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.260-265, November 09-13, 1997, San Jose, California, United States
	I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong, Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion, Proceedings of the 2000 international symposium on Physical design, p.33-38, May 2000, San Diego, California, United States
	Jason Cong , Cheng-Kok Koh, Interconnect layout optimization under higher-order RLC model, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.713-720, November 09-13, 1997, San Jose, California, United States
	Chung-wen Albert Tsao , Cheng-kok Koh, UST/DME: a clock tree router for general skew constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.359-379, July 2002
	Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing under Elmore delay, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.66-71, November 05-09, 1995, San Jose, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Andrew B. Kahng , C.-W. Albert Tsao, More practical bounded-skew clock routing, Proceedings of the 34th annual conference on Design automation, p.594-599, June 09-13, 1997, Anaheim, California, United States
	Jaewon Oh , Iksoo Pyo , Massoud Pedram, Constructing lower and upper bounded delay routing trees using linear programming, Proceedings of the 33rd annual conference on Design automation, p.401-404, June 03-07, 1996, Las Vegas, Nevada, United States
	Joe G. Xi , Wayne W.-M. Dai, Useful-skew clock routing with gate sizing for low power design, Proceedings of the 33rd annual conference on Design automation, p.383-388, June 03-07, 1996, Las Vegas, Nevada, United States
	Yu Chen , Andrew B. Kahng , Gang Qu , Alexander Zelikovsky, The associative-skew clock routing problem, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.168-172, November 07-11, 1999, San Jose, California, United States
	Masahiko Toyonaga , Keiichi Kurokawa , Takuya Yasui , Atsushi Takahashi, A practical clock tree synthesis for semi-synchronous circuits, Proceedings of the 2000 international symposium on Physical design, p.159-164, May 2000, San Diego, California, United States
	Joe G. Xi , Wayne W.-M. Dai, Jitter-tolerant clock routing in two-phase synchronous systems, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.316-320, November 10-14, 1996, San Jose, California, United States
	Andrew B. Kahng , C.-W. Albert Tsao, Practical Bounded-Skew Clock Routing, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.199-215, June/July 1997
	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997
	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Process-induced skew reduction in nominal zero-skew clock trees, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Liang Huang , Yici Cai , Qiang Zhou , Xianlong Hong , Jiang Hu , Yongqiang Lu, Clock network minimization methodology based on incremental placement, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Christoph Albrecht , Bernhard Korte , Jürgen Schietke , Jens Vygen, Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip, Discrete Applied Mathematics, v.123 n.1-3, p.103-127, 15 November 2002
	Muhammet Mustafa Ozdal , Martin D. F. Wong, Two-layer bus routing for high-speed printed circuit boards, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.1, p.213-227, January 2006
	Joe Gufeng Xi , Wayne Wei-Ming Dai, Useful-Skew Clock Routing with Gate Sizing for Low Power Design, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.163-179, June/July 1997
	A. Chakraborty , P. Sithambaram , K. Duraisami , A. Macii , E. Macii , M. Poncino, Thermal resilient bounded-skew clock tree optimization methodology, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	A. Chakraborty , K. Duraisami , A. Sathanur , P. Sithambaram , L. Benini , A. Macii , E. Macii , M. Poncino, Dynamic thermal clock skew compensation using tunable delay buffers, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Saif Ali Butt , Stefan Schmermbeck , Jurij Rosenthal , Alexander Pratsch , Eike Schmidt, System level clock tree synthesis for power optimization, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Hidenori Sato , Akira Onozawa , Hiroaki Matsuda, A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning, Proceedings of the 1996 European conference on Design and Test, p.237, March 11-14, 1996
	Ashutosh Chakraborty , Karthik Duraisami , Ashoka Sathanur , Prassanna Sithambaram , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Dynamic thermal clock skew compensation using tunable delay buffers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.639-649, June 2008
	Chia-Chun Tsai , Jan-Ou Wu , Trong-Yen Lee, GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.1, p.365-374, January 2008