Power distribution topology design

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Power distribution topology design

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 503 - 507

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Ashok Vittal	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
Malgorzata Marek-Sadowska	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 12, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Kenneth D. Boese , Andrew B. Kahng , Bernard A. McCoy , Gabriel Robins, Rectilinear Steiner trees with minimum Elmore delay, Proceedings of the 31st annual conference on Design automation, p.381-386, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196428]
	2	S. Chowdhury and J.S. Barkatullah, "Estimation of maximum currents in MOS IC logic circuits", IEEE Transactions on CAD, Vol. 9, No. 6, June 1990, pp. 642-654.
	3	S. Chowdhury and M.A. Breuer, "Optimum design of IC power/ground nets subject to reliability constraints", IEEE Transactions on CAD, Vol. 7, No.7, July 1988, pp. 787-796.
	4	Jason Cong , Kwok-Shing Leung , Dian Zhou, Performance-driven interconnect design based on distributed RC delay model, Proceedings of the 30th international conference on Design automation, p.606-611, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165065]
	5	Carver Mead , Lynn Conway, Introduction to VLSI Systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1979
	6	R. Dutta and M. Marek-Sadowska, "Algorithm for wire sizing of power and ground networks in VLSI designs", Journal of Circuits, Systems and Computers, Vol. 2, No. 2, 1992, pp. 141-157
	7	Karl-Heinz Erhard , Frank M. Johannes, Power/ground networks in VLSI: are general graphs better than trees?, Integration, the VLSI Journal, v.14 n.1, p.91-109, Nov. 1992 [doi>10.1016/0167-9260(92)90012-N]
	8	K.-H. Erhard, F.M. Johannes and R. Dachauer, "Topology optimization techniques for power/ground networks in VLSI", Proceeding of the European Design Automation Conference, 1992, pp. 362-367.
	9	T.D. Hodes, B.A. McCoy and G. Robins, "Dynamically-wiresized Elmore-based routing constructions", Proceedings of the International Symposium on Circuits and Systems, 1994, pp.463-466.
	10	Reiner Kolla, A dynamic programming approach to the power supply net sizing problem, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	11	H. Kriplani , F. Najm , I. Hajj, Maximum current estimation in CMOS circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.2-7, June 08-12, 1992, Anaheim, California, United States
	12	T. Mitsuhashi , E. S. Kuh, Power and ground network topology optimization for cell based VLSIs, Proceedings of the 29th ACM/IEEE conference on Design automation, p.524-529, June 08-12, 1992, Anaheim, California, United States
	13	Anderew S. Moulton, Laying the power and ground wires on a VLSI chip, Proceedings of the 20th conference on Design automation, p.754-755, June 27-29, 1983, Miami Beach, Florida, United States
	14	W.S. Song and L.A. Glasser, "Power distribution techniques for VLSI circuits", IEEE Journal of Solid State Circuits, Vol. 21, No. 1, February 1986, pp. 150-156.
	15	Balsha Robert Stanisic, Automatic analog power distribution synthesis in rail, Carnegie Mellon University, Pittsburgh, PA, 1993
	16	Z.A. Syed and A. E1 Gamal, "Single layer routing of power and ground networks in integrated circuits", Journal of Digital Systems, Vol. 6, No. 1, 1982, pp. 53-63.
	17	R.-S. Tsay, An exact zero-skew clock routing algorithm", IEEE Transactions on CAD, Vol. 12, 1993, pp. 242-249.
	18	E Vanoostende, E Six and H.J. de Man, "PRITI: estimation of maximal currents and current derivatives in complex CMOS circuits using activity waveforms", Proceedings of the European Design Automation Conference, 1993, pp. 347-353.

CITED BY 2

	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997