Buffer insertion and sizing under process variations for low power clock distribution

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Buffer insertion and sizing under process variations for low power clock distribution

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 491 - 496

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Joe G. Xi	National Semiconductor, Corp., Santa Clara, CA and Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA
Wayne W. M. Dai	Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 28, Citation Count: 19

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. Bakoglu. Circuits, Interconnections, and Packaging for VLSL Addison-Wesley Publishing Company, 1987.
	2	T.H. Chao, Y.C. Hsu, J.M.Ho, Kenneth D. Boese, and Andraw B. Kahng. Zero skew clock net routing. IEEE Trans. on Circuits and Systems, 39(11):799-814, 1992.
	3	D. Dobberpuhl and R. Witek. A 200mhz 64b dual-issue cmos microprocessor. In Proc. IEEE Intl. Solid-State Circuits Conf., pages 106-107, 1992.
	4	J.G. Ecker. Geometric programming methods, computations and applications. SIAM Review, 22(3):338-362, July 1980.
	5	J.P. Fishburn and A. E. Dunlop. Tilos: A posynomial programming approach to transistor sizing. In IEEE Intl. Conf. on CAD, pages 326-328, 1985.
	6	Michael A. B. Jackson , Arvind Srinivasan , E. S. Kuh, Clock routing for high-performance ICs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.573-579, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123406]
	7	Satyamurthy Pullela, Noel Menezes, Junaid Omar, and Lawrence T. Pillage. Skew and delay optimization for reliable buffered clock trees. In Proc. of IEEE Intl. Conf. on CAD, pages 556-562, 1993.
	8	Satyamurthy Pullela , Noel Menezes , Lawrence T. Pillage, Reliable non-zero skew clock trees using wire width optimization, Proceedings of the 30th international conference on Design automation, p.165-170, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164653]
	9	Masakazu Shoji. Elimination of process-dependent clock skew in cmos vlsi. IEEE Journal of Solid-State Circuits, sc-21(1):875-880, 1986.
	10	Ren-Song Tsay. An exact zero-skew clock routing algorithm. IEEE Trans. on CAD, 12(3):242-249, 1993.
	11	Joe G. Xi and Wayne W.M. Dai. Buffer insertion and sizing under process variations for low power clock distribution. In Technical Report, UCSC-CRL-95-12, University of California, Santa Cruz., 1995.
	12	Qing Zhu , Wayne Wei-Ming Dai, Perfect-balance planar clock routing with minimal path-length, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.473-476, November 1992, Santa Clara, California, United States
	13	Qing Zhu , Wayne W.-M. Dai , Joe G. Xi, Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.628-633, November 07-11, 1993, Santa Clara, California, United States

CITED BY 19

	Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.341-388, July 1998
	Jun-Dong Cho, A min-cost flow based min-cost rectilinear Steiner distance-preserving tree construction, Proceedings of the 1997 international symposium on Physical design, p.82-87, April 14-16, 1997, Napa Valley, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Joe G. Xi , Wayne W.-M. Dai, Useful-skew clock routing with gate sizing for low power design, Proceedings of the 33rd annual conference on Design automation, p.383-388, June 03-07, 1996, Las Vegas, Nevada, United States
	X. Zeng , D. Zhou , Wei Li, Buffer insertion for clock delay and skew minimization, Proceedings of the 1999 international symposium on Physical design, p.36-41, April 12-14, 1999, Monterey, California, United States
	I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong, Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion, Proceedings of the 2000 international symposium on Physical design, p.33-38, May 2000, San Diego, California, United States
	Jaewon Oh , Iksoo Pyo , Massoud Pedram, Constructing lower and upper bounded delay routing trees using linear programming, Proceedings of the 33rd annual conference on Design automation, p.401-404, June 03-07, 1996, Las Vegas, Nevada, United States
	Joe G. Xi , Wayne W.-M. Dai, Jitter-tolerant clock routing in two-phase synchronous systems, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.316-320, November 10-14, 1996, San Jose, California, United States
	Bing Lu , Jiang Hu , Gary Ellis , Haihua Su, Process variation aware clock tree routing, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Kai Wang , Malgorzata Marek-Sadowska, Buffer sizing for clock power minimization subject to general skew constraints, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Andrew B. Kahng , C.-W. Albert Tsao, Practical Bounded-Skew Clock Routing, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.199-215, June/July 1997
	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997
	Hailin Jiang , Kai Wang , Malgorzata Marek-Sadowska, Clock skew bounds estimation under power supply and process variations, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Monica Donno , Enrico Macii , Luca Mazzoni, Power-aware clock tree planning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Joe Gufeng Xi , Wayne Wei-Ming Dai, Useful-Skew Clock Routing with Gate Sizing for Low Power Design, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.163-179, June/July 1997
	L. Benini , P. Vuillod , A. Bogliolo , G. De Micheli, Clock Skew Optimization for Peak Current Reduction, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.117-130, June/July 1997
	G. Venkataraman , N. Jayakumar , J. Hu , P. Li , Sunil Khatri , Anand Rajaram , P. McGuinness , C. Alpert, Practical techniques to reduce skew and its variations in buffered clock networks, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.592-596, November 06-10, 2005, San Jose, CA
	Yanfeng Wang , Qiang Zhou , Yici Cai , Jiang Hu , Xianlong Hong , Jinian Bian, Low power clock buffer planning methodology in F-D placement for large scale circuit design, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Inna Vaisband , Ran Ginosar , Avinoam Kolodny , Eby G. Friedman, Power efficient tree-based crosslinks for skew reduction, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA