Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm

Full text

Pdf (272 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 474 - 479

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

P. Feldmann	AT&T Bell Laboratories, Murray Hill, NJ
R. W. Freund	AT&T Bell Laboratories, Murray Hill, NJ

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 31, Citation Count: 48

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/217474.217573 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	V. Raghavan , J. E. Bracken , R. A. Rohrer, AWESpice: a general tool for the accurate and efficient simulation of interconnect problems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.87-92, June 08-12, 1992, Anaheim, California, United States
	2	L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, vol. 9, pp. 352-366, Apr. 1990.
	3	V. Raghavan, R. A. Rohrer, L. T. Pillage, J. Y. Lee, J. E. Bracken, and M. M. Alaybeyi, "AWE-inspired," in Proc. IEEE Custom Integrated Circuits Conf., May 1993.
	4	Peter Feldmann , Roland W. Freund, Efficient linear circuit analysis by Pade´ approximation via the Lanczos process, Proceedings of the conference on European design automation, p.170-175, September 19-23, 1994, Grenoble, France
	5	R. W. Freund , P. Feldmann, Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.404-411, November 06-10, 1994, San Jose, California, United States
	6	Jiri Vlach , Kishore Singhal, Computer Methods for Circuit Analysis and Design, John Wiley & Sons, Inc., New York, NY, 1983
	7	C. Lanczos, "An iteration method for the solution of the eigenvalue problem of linear differential and integral operators," J. Res. Nat. Bur. Standards, vol. 45, pp. 255-282, 1950.
	8	J. I. Aliaga, D. L. Boley, R. W. Freund, and V. Hern~ndez, "A Lanczos-type algorithm for multiple starting vectors," Numerical Analysis Manuscript, AT&T Bell Laboratories, Murray Hill, NJ, 1995.

CITED BY 48

	Jaijeet Roychowdhury, Reduced-order modelling of linear time-varying systems, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.92-95, November 08-12, 1998, San Jose, California, United States
	Peter Feldmann , Roland W. Freund, Circuit noise evaluation by Padé approximation based model-reduction techniques, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.132-138, November 09-13, 1997, San Jose, California, United States
	R. W. Freund , P. Feldmann, Reduced-order modeling of large linear passive multi-terminal circuits using matrix-padé approximation, Proceedings of the conference on Design, automation and test in Europe, p.530-537, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Kenneth L. Shepard, Design methodologies for noise in digital integrated circuits, Proceedings of the 35th annual conference on Design automation, p.94-99, June 15-19, 1998, San Francisco, California, United States
	Haifang Liao , Wayne Wei-Ming Dai, Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.704-709, November 05-09, 1995, San Jose, California, United States
	Luca Daniel , Joel Phillips, Model order reduction for strictly passive and causal distributed systems, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Kevin J. Kerns , Ivan L. Wemple , Andrew T. Yang, Stable and efficient reduction of substrate model networks using congruence transforms, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.207-214, November 05-09, 1995, San Jose, California, United States
	Tuyen V. Nguyen , Jing Li, Multipoint Padé approximation using a rational block Lanczos algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.72-75, November 09-13, 1997, San Jose, California, United States
	Tilmann Stöhr , Markus Alt , Asmus Hetzel , Jürgen Koehl, Analysis, reduction and avoidance of crosstalk on VLSI chips, Proceedings of the 1998 international symposium on Physical design, p.211-218, April 06-08, 1998, Monterey, California, United States
	Bernard N. Sheehan, ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization, Proceedings of the 36th ACM/IEEE conference on Design automation, p.17-21, June 21-25, 1999, New Orleans, Louisiana, United States
	Anirudh Devgan, Efficient coupled noise estimation for on-chip interconnects, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.147-151, November 09-13, 1997, San Jose, California, United States
	Kevin J. Kerns , Andrew T. Yang, Preservation of passivity during RLC network reduction via split congruence transformations, Proceedings of the 34th annual conference on Design automation, p.34-39, June 09-13, 1997, Anaheim, California, United States
	Zhanhai Qin , Chung-Kuan Cheng, Realizable parasitic reduction using generalized Y-Δ transformation, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, PRIMA: passive reduced-order interconnect macromodeling algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.58-65, November 09-13, 1997, San Jose, California, United States
	Kevin J. Kerns , Andrew T. Yang, Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations, Proceedings of the 33rd annual conference on Design automation, p.280-285, June 03-07, 1996, Las Vegas, Nevada, United States
	L. Miguel Silveira , Mattan Kamon , Ibrahim Elfadel , Jacob White, A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.288-294, November 10-14, 1996, San Jose, California, United States
	Bernard N. Sheehan, TICER: realizable reduction of extracted RC circuits, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.200-203, November 07-11, 1999, San Jose, California, United States
	Yehea I. Ismail, Efficient model order reduction via multi-node moment matching, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.767-774, November 10-14, 2002, San Jose, California
	Luca Daniel , Alberto Sangiovanni-Vincentelli , Jacob White, Techniques for including dielectrics when extracting passive low-order models of high speed interconnect, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
	Mattan Kamon , Steve McCormick , Ken Sheperd, Interconnect parasitic extraction in the digital IC design methodology, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.223-231, November 07-11, 1999, San Jose, California, United States
	R. W. Freund , P. Feldmann, Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.280-287, November 10-14, 1996, San Jose, California, United States
	Vasant B. Rao , Jeffrey P. Soreff , Ravichander Ledalla , Fred L. Yang, Aggressive crunching of extracted RC netlists, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Zhanhai Qin , Chung-Kuan Cheng, RCLK-VJ network reduction with Hurwitz polynomial approximation, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Min Xu , Lei He, An efficient model for frequency-dependent on-chip inductance, Proceedings of the 11th Great Lakes symposium on VLSI, p.115-120, March 2001, West Lafayette, Indiana, United States
	Anirudh Devgan , Peter R. O'Brien, Realizable reduction for RC interconnect circuits, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.204-207, November 07-11, 1999, San Jose, California, United States
	Ching-Han Tsai , Sung-Mo Kang, Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction, Proceedings of the 37th conference on Design automation, p.750-755, June 05-09, 2000, Los Angeles, California, United States
	Al Dunlop , Alper Demir , Peter Feldmann , Sharad Kapur , David Long , Robert Melville , Jaijeet Roychowdhury, Tools and methodology for RF IC design, Proceedings of the 35th annual conference on Design automation, p.414-420, June 15-19, 1998, San Francisco, California, United States
	Yehea I. Ismail, Improved model-order reduction by using spacial information in moments, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.900-908, October 2003
	N. Wong , V. Balakrishnan , C.-K. Koh, Passivity-preserving model reduction via a computationally efficient project-and-balance scheme, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	A. El Guennouni , K. Jbilou , H. Sadok, The block Lanczos method for linear systems with multiple right-hand sides, Applied Numerical Mathematics, v.51 n.2-3, p.243-256, November 2004
	Zhengyong Zhu , Khosro Rouz , Manjit Borah , Chung-Kuan Cheng , Ernest S. Kuh, Efficient transient simulation for transistor-level analysis, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Seongkyun Shin , Yungseon Eo , William R. Eisenstadt , Jongin Shim, Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.395-407, April 2004
	Zhaojun Bai, Krylov subspace techniques for reduced-order modeling of large-scale dynamical systems, Applied Numerical Mathematics, v.43 n.1-2, p.9-44, October 2002
	Zhengyong Zhu , Rui Shi , Chung-Kuan Cheng , Ernest S. Kuh, An unconditional stable general operator splitting method for transistor level transient analysis, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Lihong Feng, Parameter independent model order reduction, Mathematics and Computers in Simulation, v.68 n.3, p.221-234, 1 May 2005
	Man-Chung Yeung , Daniel Boley, Transpose-free multiple Lanczos and its application in Padé approximation, Journal of Computational and Applied Mathematics, v.177 n.1, p.101-127, 1 May 2005
	Dian Zhou , Rui-Ming Li, Design and verification of high-speed VLSI physical design, Journal of Computer Science and Technology, v.20 n.2, p.147-165, March 2005
	K. L. Shepard , V. Narayanan , P. C. Elmendorf , Gutuan Zheng, Global harmony: coupled noise analysis for full-chip RC interconnect networks, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.139-146, November 09-13, 1997, San Jose, California, United States
	Roland W. Freund, Passive reduced-order models for interconnect simulation and their computation via Krylov-subspace algorithms, Proceedings of the 36th ACM/IEEE conference on Design automation, p.195-200, June 21-25, 1999, New Orleans, Louisiana, United States
	Zhenhai Zhu , Joel Phillips, Random sampling of moment graph: a stochastic Krylov-reduction algorithm, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	R. W. Freund, SPRIM: structure-preserving reduced-order interconnect macromodeling, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.80-87, November 07-11, 2004
	P. Feldmann , F. Liu, Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.88-92, November 07-11, 2004
	Lun Ye , Foong-Charn Chang , Peter Feldmann , Nagaraj Ns , Rakesh Chadha , Frank Cano, Chip-level verification for parasitic coupling effects in deep-submicron digital designs, Proceedings of the conference on Design, automation and test in Europe, p.128-es, January 1999, Munich, Germany
	Janet M. Wang , Qingjian Yu , Ernest S. Kuh, Coupled noise estimation for distributed RC interconnect model, Proceedings of the conference on Design, automation and test in Europe, p.129-es, January 1999, Munich, Germany
	Bernard N. Sheehan, Projective convolution: RLC model-order reduction using the impulse response, Proceedings of the conference on Design, automation and test in Europe, p.130-es, January 1999, Munich, Germany
	Sheldon X. -D. Tan, A General S-Domain Hierarchical Network Reduction Algorithm, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.650, November 09-13, 2003
	Peter Feldmann, Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals, Proceedings of the conference on Design, automation and test in Europe, p.20944, February 16-20, 2004