Performance analysis of embedded software using implicit path enumeration

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Performance analysis of embedded software using implicit path enumeration

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 456 - 461

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Yau-Tsun Steven Li	Department of Electrical Engineering, Princeton University, NJ
Sharad Malik	Department of Electrical Engineering, Princeton University, NJ

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 23, Citation Count: 34

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 34

	L. M. Reyneri , F. Cucinotta , A. Serra , L. Lavagno, A hardware/software co-design flow and IP library based on simulink, Proceedings of the 38th conference on Design automation, p.593-598, June 2001, Las Vegas, Nevada, United States
	Ti-Yen Yen , Wayne Wolf, Performance estimation for real-time distributed embedded systems, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Neal K. Bambha , Shuvra S. Bhattacharyya , Jürgen Teich , Eckart Zitzler, Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors, Proceedings of the ninth international symposium on Hardware/software codesign, p.243-248, April 2001, Copenhagen, Denmark
	Yau-Tsun Steven Li , Sharad Malik , Andrew Wolfe, Performance estimation of embedded software with instruction cache modeling, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.3, p.257-279, July 1999
	Neal K. Bambha , Shuvra S. Bhattacharyya, A joint power/performance optimization algorithm for multiprocessor systems using a period graph construct, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	P. Giusto , G. Martin , E. Harcourt, Reliable estimation of execution time of embedded software, Proceedings of the conference on Design, automation and test in Europe, p.580-589, March 2001, Munich, Germany
	Yau-Tsun Steven Li , Sharad Malik , Andrew Wolfe, Performance estimation of embedded software with instruction cache modeling, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.380-387, November 05-09, 1995, San Jose, California, United States
	Rajesh K. Gupta, Analysis of operation delay and execution rate constraints for embedded systems, Proceedings of the 33rd annual conference on Design automation, p.601-604, June 03-07, 1996, Las Vegas, Nevada, United States
	Yau-Tsun Steven Li , Sharad Malik , Andrew Wolfe, Performance estimation of embedded software with instruction cache modeling, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Friedhelm Stappert , Andreas Ermedahl , Jakob Engblom, Efficient longest executable path search for programs with complex flows and pipeline effects, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
	Andreas Ermedahl , Friedhelm Stappert , Jakob Engblom, Clustered calculation of worst-case execution times, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	Tobias Schuele , Klaus Schneider, Abstraction of assembler programs for symbolic worst case execution time analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	P. Eles , K. Kuchcinski , Z. Peng , A. Doboli , P. Pop, Scheduling of conditional process graphs for the synthesis of embedded systems, Proceedings of the conference on Design, automation and test in Europe, p.132-139, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Kei Suzuki , Alberto Sangiovanni-Vincentelli, Efficient software performance estimation methods for hardware/software codesign, Proceedings of the 33rd annual conference on Design automation, p.605-610, June 03-07, 1996, Las Vegas, Nevada, United States
	Ti-Yen Yen , Wayne Wolf, Performance Estimation for Real-Time Distributed Embedded Systems, IEEE Transactions on Parallel and Distributed Systems, v.9 n.11, p.1125-1136, November 1998
	Márcio Seiji Oyamada , Felipe Zschornack , Flávio Rech Wagner, Accurate software performance estimation using domain classification and neural networks, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	A. Siebenborn , O. Bringmann , W. Rosenstiel, Worst-case performance analysis of parallel, communicating software processes, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Andreas Ermedahl , Friedhelm Stappert , Jakob Engblom, Clustered Worst-Case Execution-Time Calculation, IEEE Transactions on Computers, v.54 n.9, p.1104-1122, September 2005
	Daniel Menard , Daniel Chillet , Olivier Sentieys, Floating-to-fixed-point conversion for digital signal processors, EURASIP Journal on Applied Signal Processing, v.2006 n.1, p.77-77, 01 January
	Christian Ferdinand , Reinhard Wilhelm, Efficient and Precise Cache Behavior Prediction for Real-TimeSystems, Real-Time Systems, v.17 n.2-3, p.131-181, Nov. 1999
	Henrik Theiling , Christian Ferdinand , Reinhard Wilhelm, Fast and Precise WCET Prediction by Separated Cache andPath Analyses, Real-Time Systems, v.18 n.2-3, p.157-179, May 2000
	Bassam Tabbara , Enrica Filippi , Luciano Lavagno, Fast hardware-software co-simulation using VHDL models, Proceedings of the conference on Design, automation and test in Europe, p.64-es, January 1999, Munich, Germany
	Ali Dasdan , Anmol Mathur , Rajesh K. Gupta, RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems, Proceedings of the 1997 European conference on Design and Test, p.2, March 17-20, 1997
	Rajesh K. Gupta, Operation Serializability for Embedded Systems, Proceedings of the 1996 European conference on Design and Test, p.108, March 11-14, 1996
	W. Hardt , W. Rosenstiel, Speed-up estimation for HW/SW-systems, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.36, March 18-20, 1996
	Junwei Hou , Wayne Wolf, Process Partitioning for Distributed Embedded Systems, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.70, March 18-20, 1996
	Reiner W. Hartenstein , Juergen Becker, Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators, Proceedings of the 5th International Workshop on Hardware/Software Co-Design, p.141, March 24-26, 1997
	A. Balboni , W. Fornaciari , D. Sciuto , M. Vincenzi, The use of a virtual instruction set for the software synthesis of Hw/Sw embedded systems, Proceedings of the 9th international symposium on System synthesis, p.77, November 06-08, 1996
	Alexander Maxiaguine , Simon Künzli , Lothar Thiele, Workload Characterization Model for Tasks with Variable Execution Demand, Proceedings of the conference on Design, automation and test in Europe, p.21040, February 16-20, 2004
	Marcio Seiji Oyamada , Felipe Zschornack , Flávio Rech Wagner, Applying neural networks to performance estimation of embedded software, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.1-2, p.224-240, January, 2008
	Reinhard Wilhelm , Jakob Engblom , Andreas Ermedahl , Niklas Holsti , Stephan Thesing , David Whalley , Guillem Bernat , Christian Ferdinand , Reinhold Heckmann , Tulika Mitra , Frank Mueller , Isabelle Puaut , Peter Puschner , Jan Staschulat , Per Stenström, The worst-case execution-time problem—overview of methods and survey of tools, ACM Transactions on Embedded Computing Systems (TECS), v.7 n.3, p.1-53, April 2008
	Eric Keller , Evan Green, Virtualizing the data plane through source code merging, Proceedings of the ACM workshop on Programmable routers for extensible services of tomorrow, August 22-22, 2008, Seattle, WA, USA
	David C. Pheanis , John A. Jackson , Lance G. Johnson, DynaTest and beyond: From dynamic testing to automated error-prevention and error-detection, Journal of Computational Methods in Sciences and Engineering, v.5 n.1 Supplement, p.1-12, January 2005
	Carsten Albrecht , Roman Koch , Thilo Pionteck , Erik Maehle , Michael Werner , Rudolf Fuchsen, WCET determination tool for embedded systems software, Proceedings of the 1st international conference on Simulation tools and techniques for communications, networks and systems & workshops, March 03-07, 2008, Marseille, France