Direct performance-driven placement of mismatch-sensitive analog circuits

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Direct performance-driven placement of mismatch-sensitive analog circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 445 - 449

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

K. Lampaert	Katholieke Universiteit Leuven, Dep. Elektrotechniek, ESAT-MICAS, Kardinaal Mercierlaan 94, B-3001 Heverlee, Belgium
G. Gielen	National Fund of Scientific Research and Katholieke Universiteit Leuven, Dep. Elektrotechniek, ESAT-MICAS, Kardinaal Mercierlaan 94, B-3001 Heverlee, Belgium
W. Sansen	Katholieke Universiteit Leuven, Dep. Elektrotechniek, ESAT-MICAS, Kardinaal Mercierlaan 94, B-3001 Heverlee, Belgium

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 5, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	V. K. zu Bexten, C. Moraga, R. Klinke, "ALSYN: flexible rule-based layout synthesis for analog IC's," IEEE J. of Solid State Circuits, vol. 28, no. 3, March 1993.
	3	U. Choudhury and A. Sangiovanni-Vincentelli, "Automatic Generation of Parasitic Constraints for Performance- Constrained Physical Design of Analog Circuits," IEEE Trans. Computer-Aided Design, vol. 12, no. 2, pp. 208-224, February 1993.
	4	Edoardo Charbon , Enrico Malavasi , Alberto Sangiovanni-Vincentelli, Generalized constraint generation for analog circuit design, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.408-414, November 07-11, 1993, Santa Clara, California, United States
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	6	M. J. M. Pelgrom, A. C. J. Duinmaijer, A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. of Solid State Circuits, vol. SC-24,no. 5, pp. 1433-1440, October 1989.
	7	M. Steyaert, R. Roovers and J. Craninckx, "A 110 MHz 8 bit CMOS Interpolating A/D converter," Proc IEEE Custom Integrated Circ. Conf., pp. 28.1.1-28.1.4 May 1993.
	8	E. Peeters, Ghafoor K., "Design of a Fully Differential High- Speed CMOS Amplifier," KU Leuven Masters Thesis. June 1993.