Advanced verification techniques based on learning

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Advanced verification techniques based on learning

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 420 - 426

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Jawahar Jain	Fujitsu Laboratories of America, 77 Rio Robles, San Jose CA
Rajarshi Mukherjee	Fujitsu Laboratories of America, 77 Rio Robles, San Jose CA and Dept. of Electrical and Computer Engineering, University of Texas at Austin, Austin TX
Masahiro Fujita	Fujitsu Laboratories of America, 77 Rio Robles, San Jose CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 13, Citation Count: 21

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Daniel Brand, Verification of large synthesized designs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.534-537, November 07-11, 1993, Santa Clara, California, United States
	3	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
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	6	Fujita M., Fujisawa H., Kawato N., "Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams", ICCAD, 1988, pp. 2-5.
	7	Wolfgang Kunz , Dhiraj K. Pradhan, Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.816-825, September 20-24, 1992
	8	Wolfgang Kunz, HANNIBAL: an efficient tool for logic verification based on recursive learning, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.538-543, November 07-11, 1993, Santa Clara, California, United States
	9	Malik S. et al., "Logic Verification using Binary Decision Diagrams in a Logic Synthesis Environment", ICCAD, 1988, pp. 6-9.
	10	Mukherjee R., Jain J., Pradhan D. K., "Functional Learning: A new approach to learning in digital circuits", IEEE VLSI Test Symp., pp. 122-127, April 1994.
	11	R. Mukherjee , J. Jain , M. Fujita, VERIFUL: VERIfication using FUnctional Learning, Proceedings of the 1995 European conference on Design and Test, p.444, March 06-09, 1995
	12	Jain J., Mukherjee R., Fujita M., "Verification Techniques Based on Functional Learning", Technical Report No. FLA- CPS95-01, Fujitsu Laboratories of America, 1995.
	13	Richard Rudell, Dynamic variable ordering for ordered binary decision diagrams, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.42-47, November 07-11, 1993, Santa Clara, California, United States
	14	Schulz M., Trischler E., Safert T., "SOCRATES: A highly efficient automatic test pattern generation system", IEEE Trans. on CAD, vol. 7, Jan. 1988, pp. 126-137.
	15	Thomas R. Shiple , Ramin Hojati , Alberto L. Sangiovanni-Vincentelli , Robert K. Brayton, Heuristic minimization of BDDs using don't cares, Proceedings of the 31st annual conference on Design automation, p.225-231, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196360]

CITED BY 21

	R. Bahar , M. Burns , G. Hachtel , E. Macii , H. Shin , F. Somenzi, Symbolic computation of logic implications for technology-dependent low-power synthesis, Proceedings of the 1996 international symposium on Low power electronics and design, p.163-168, August 12-14, 1996, Monterey, California, United States
	Andreas Kuehlmann , Cornelis A. J. van Eijk, Combinational and sequential equivalence checking, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Amit Narayan , Jawahar Jain , M. Fujita , A. Sangiovanni-Vincentelli, Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.547-554, November 10-14, 1996, San Jose, California, United States
	E. Goldberg , M. Prasad , R. Brayton, Using SAT for combinational equivalence checking, Proceedings of the conference on Design, automation and test in Europe, p.114-121, March 2001, Munich, Germany
	Rajarshi Mukherjee , Jawahar Jain , Koichiro Takayama , Masahiro Fujita, Automatic partitioning for efficient combinatorial verification, Proceedings of the 2000 conference on Asia South Pacific design automation, p.67-72, January 2000, Yokohama, Japan
	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	Armin Biere , Wolfgang Kunz, SAT and ATPG: Boolean engines for formal hardware verification, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.782-785, November 10-14, 2002, San Jose, California
	Paul Tafertshofer , Andreas Ganz , Manfred Henftling, A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.648-655, November 09-13, 1997, San Jose, California, United States
	Jerry R. Burch , Vigyan Singhal, Tight integration of combinational verification methods, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.570-576, November 08-12, 1998, San Jose, California, United States
	Aarti Gupta , Malay Ganai , Chao Wang , Zijiang Yang , Pranav Ashar, Learning from BDDs in SAT-based bounded model checking, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Dominik Stoffel , Wolfgang Kunz, Verification of integer multipliers on the arithmetic bit level, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Rajarshi Mukherjee , Jawahar Jain , Koichiro Takayama , Jacob A. Abraham , Donald S. Fussell , Masahiro Fujita, Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table, Formal Methods in System Design, v.21 n.1, p.95-101, July 2002
	Andreas Kuehlmann , Florian Krohm, Equivalence checking using cuts and heaps, Proceedings of the 34th annual conference on Design automation, p.263-268, June 09-13, 1997, Anaheim, California, United States
	Yusuke Matsunaga, An efficient equivalence checker for combinational circuits, Proceedings of the 33rd annual conference on Design automation, p.629-634, June 03-07, 1996, Las Vegas, Nevada, United States
	S. Reda , A. Salem, Combinational equivalence checking using Boolean satisfiability and binary decision diagrams, Proceedings of the conference on Design, automation and test in Europe, p.122-126, March 2001, Munich, Germany
	Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , Forrest Brewer , Chung-Yang Huang, AQUILA: An Equivalence Checking System for Large Sequential Designs, IEEE Transactions on Computers, v.49 n.5, p.443-464, May 2000
	Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , Forrest Brewer , Chung-Yang Huang, AQUILA: An Equivalence Checking System for Large Sequential Designs, IEEE Transactions on Computers, v.49 n.5, p.443-464, May 2000
	Masahiro Fujita, Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.4, p.610-626, October 2005
	Jaehong Park , Carl Pixley , Michael Burns , Hyunwoo Cho, An Efficient Logic Equivalence Checker for Industrial Circuits, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.91-106, Feb/April 2000
	Rajarshi Mukherjee , Jawahar Jain , Koichiro Takayama , Masahiro Fujita , Jacob A. Abraham , Donald S. Fussell, An efficient filter-based approach for combinational verification, Proceedings of the conference on Design, automation and test in Europe, p.31-es, January 1999, Munich, Germany
	João Marques-Silva , Thomas Glass, Combinational equivalence checking using satisfiability and recursive learning, Proceedings of the conference on Design, automation and test in Europe, p.33-es, January 1999, Munich, Germany