Deriving efficient area and delay estimates by modeling layout tools

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Deriving efficient area and delay estimates by modeling layout tools

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 402 - 407

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Donald S. Gelosh	Air Force Institute of Technology, Wright-Patterson AFB, OH
Dorothy E. Setliff	Department of Electrical Engineering, University of Pittsburgh, Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 5, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Buchanan, B. and Shortliffe, E. Rule-Based Expert Systems, (Beading: Addison-Wesley, 1984) pp. 247-262.
	2	Hsieh, Yea-Wing, "Architectural Synthesis Via VHDL" (M.S. thesis, the University of Pittsburgh, 1992).
	3	M. J. Irwin , R. M. Owens, A comparison of four two-dimensional gate matrix layout tools, Proceedings of the 26th ACM/IEEE conference on Design automation, p.698-701, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74507]
	4	Sungho Kang, Linear ordering and application to placement, Proceedings of the 20th conference on Design automation, p.457-464, June 27-29, 1983, Miami Beach, Florida, United States
	5	Kurdahi, F.J. and Parker, A.C., "Techniques for Area Estimation of VLSI Layouts," IEEE Transactions on Computer- Aided Design, vol. 8, no. 1, (Jan. 1989), pp. 81-92.
	6	Landman, B. and Russo, R., "On a Pin Versus Block Relationship for Partition of Logic Graphs," IEEE Transactions on Computers, vol. C-20, pg. 1469, 1971.
	7	Personal communication with Steven P. Levitan, Assistant Professor, Department of Electrical Engineering, University of Pittsburgh, PA., September 6, 1993.
	8	MCNC, Center for Microelectronic Systems Technologies, 3021 Cornwallis Road, P.O. Box 12889, Research Triangle Park, N.C. 27709.
	9	Michael C. McFarland , Alice C. Parker , Raul Camposano, Tutorial on high-level synthesis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.330-336, June 12-15, 1988, Atlantic City, New Jersey, United States
	10	McFarland, M.C., Parker, A.C., and Camposano, R., "The High-Level Synthesis of Digital Systems," Proceedings of the IEEE, Vol. 78, No. 2 (February 1990), pp. 301-317.
	11	Mehrdad Nourani , Christos Papachristou, A layout estimation algorithm for RTL datapaths, Proceedings of the 30th international conference on Design automation, p.285-291, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164895]
	12	John K. Ousterhout , Gordon T. Hamachi , Robert N. Mayo , Walter S. Scott , George S. Taylor, Magic: A VLSI layout system, Proceedings of the 21st conference on Design automation, p.152-159, June 25-27, 1984, Albuquerque, New Mexico, United States
	13	John Foster Provost, Policies for the selection of bias in inductive machine learning, University of Pittsburgh, Pittsburgh, PA, 1992
	14	Ramachandran, C. and Kurdahi, F.J., "TELE: A Timing Evaluator Using Layout Estimation for High Level Applications," Proceedings of the European Design Automation Conference, 1992.
	15	Terman, C.J. "Simulation Tools for Digital LSI Design" (Ph.D. thesis MIT Laboratory of Technology for Computer Science, 1983).
	16	Weiss, Sholom M. and Kulikowski, Casimir A., Computer Systems That Learn, (San Mateo: Morgan Kaufmann, 1991).