Performance driven global routing and wiring rule generation for high speed PCBs and MCMs

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Performance driven global routing and wiring rule generation for high speed PCBs and MCMs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 381 - 387

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Sharad Mehrotra	IBM Corporation, 11400 Burnet Road, Austin, TX
Paul Franzon	Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC
Michael Steer	Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 3

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E.E. Davidson and G.A. Katopis. Package Electrical Design. In R.R. Tummala and E.J. Rymaszewski, editors, Microlectronics Semiconductor Handbook, chapter 3. Van Nostrand Reinhold, 1989.
	2	Stephen W. Director , Andrzej J. Strojwas , Wojciech Maly, VLSI Design for Manufacturing: Yield Enhancement, Kluwer Academic Publishers, Norwell, MA, 1989
	3	P. D. Franzon. Chapter 11. In D. A. Doane and P. D. Franzon, editors, Multichip Module Technologies and Alternatives: The Basics. Van Nostrand Reinhold, 1992.
	4	Rohini Gupta , Lawrence T. Pillage, OTTER: optimal termination of transmission lines excluding radiation, Proceedings of the 31st annual conference on Design automation, p.640-645, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196600]
	5	Intel Corporation. Pentium Processor/82~30 PClset Open Design Guide, 1993.
	6	Peter Lancaster and Kestutis Salkauskas. Curve and surface fitting : An introduction. Academic Press, 1986.
	7	Jaebum Lee , Eugene Shragowitz , David Poli, Bounds on net lengths for high-speed PCB, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.73-76, November 07-11, 1993, Santa Clara, California, United States
	8	Thomas Lengauer, Combinatorial algorithms for integrated circuit layout, John Wiley & Sons, Inc., New York, NY, 1990
	9	M. D. McKay, R. J. Beckman, and W. J. Conover. A comparison of three methods for selecting values of input variables in the analysis of output from a computer code. Technometrics, 21(2):239-245, May 1979.
	10	Sharad Mehrotra. Automated synthesis of high speed digital circuits and package-level interconnect. PhD thesis, North Carolina State University, 1994.
	11	L. T. Pillage and R. A. Rohrer. Asymptotic Waveform Evaluation for timing analysis. IEEE Trans. on CAD, 9:pp. 352-366, 1990.
	12	P. Raghavan and C. D. Thompson. Multiterminal global routing: A deterministic approximation. Algorithmica, 6:73-82, 1991.
	13	S. Simovich, S. Mehrotra, P. Franzon, and M. Steer. Delay and reflection noise macromodeling for signal integrity management of PCBs and MCMs. IEEE Trans. on CPMT, 17(1):15-21, 1994.
	14	Slobodan Simovich. A methodology for automated simulation-based electrical characterization and design of high-speed systems. PhD thesis, North Carolina State University, 1994.
	15	M. Sriram and S. M. Kang. Phyiscal Design of Multi Chip Modules. Kluwer Academic Press, 1993.
	16	D. Theune , R. Thiele , T. Lengauer , A. Feldmann, HERO: hierarchical EMC-constrained routing, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.468-472, November 1992, Santa Clara, California, United States

CITED BY 3

	Jason Cong , Patrick H. Madden, Performance driven multi-layer general area routing for PCB/MCM designs, Proceedings of the 35th annual conference on Design automation, p.356-361, June 15-19, 1998, San Francisco, California, United States
	Bernie Sheehan, An AWE technique for fast printed circuit board delays, Proceedings of the 33rd annual conference on Design automation, p.539-543, June 03-07, 1996, Las Vegas, Nevada, United States
	Rohini Gupta , Lawrence T. Pileggi, Constrained multivariable optimization of transmission lines with general topologies, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.130-137, November 05-09, 1995, San Jose, California, United States