Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures

Full text

Pdf (204 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 376 - 380

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

L. Miguel Silveira	Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA
Mattan Kamon	Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA
Jacob White	Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 45

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/217474.217558 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Lawrence T. Pillage and Ronald A. Rohrer. Asymptotic Waveform Evaluation for Timing Analysis. IEEE Trans. CAD, 9(4):352-366, April 1990.
	2	Peter Feldmann , Roland W. Freund, Efficient linear circuit analysis by Pade´ approximation via the Lanczos process, Proceedings of the conference on European design automation, p.170-175, September 19-23, 1994, Grenoble, France
	3	M. Kamon, M. J. Tsuk, and J. White. Fasthenry: A multipole-accelerated 3-d inductance extraction program. IEEE Transactions on Microwave Theory and Techniques, 42(9):1750-1758, September 1994.
	4	Youcef Saad , Martin H Schultz, GMRES: a generalized minimal residual algorithm for solving nonsymmetric linear systems, SIAM Journal on Scientific and Statistical Computing, v.7 n.3, p.856-869, July 1986 [doi>10.1137/0907058]
	5	A. E. Ruehli. Inductance calculations in a complex integrated circuit environment. IBM J. Res. Develop., 16:470-481, September 1972.
	6	L. Greengard. The Rapid Evaluation of Potential Fields in Particle Systems. M.I.T. Press, Cambridge, Massachusetts, 1988.
	7	G. A. Baker Jr. The theory and application of the pad~ approximant methods. In K. A. Brueckner, editor, Advances in Theoretical Physics, vol. 1, pages 1-58. Academic Press, New York, 1965.
	8	W. B. Gragg and A. Lindquist. On the partial realization problem. Linear Algebra and its Applications, 50:277-319, 1983.
	9	K. Gallivan, E. Grimme, and P. Van Dooren. Asymptotic Waveform Evaluation via a Lanczos Method. Applied Mathematics Letters, 7(5):75-80, 1994.
	10	K. Gallivan, E. Grimme, and P. Van Dooren. Multipoint pad6 approximants of large-scale systems via a two-sided rational krylov algorithm. In 33~a IEEE Conference on Decision and Control, December 1994.

CITED BY 45

	Tao Lin , Emrah Acar , Lawrence Pileggi, h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.19-25, November 08-12, 1998, San Jose, California, United States
	Ying Liu , Lawrence T. Pileggi , Andrzej J. Strojwas, Model order-reduction of RC(L) interconnect including variational analysis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.201-206, June 21-25, 1999, New Orleans, Louisiana, United States
	Q. Su , V. Balakrishnan , C.-K. Koh, A factorization-based framework for passivity-preserving model reduction of RLC systems, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Joel R. Phillips, Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.96-102, November 08-12, 1998, San Jose, California, United States
	Mattan Kamon , Steven S. Majors, Package and interconnect modeling of the HFA3624, a 2.4GHz RF to IF converter, Proceedings of the 33rd annual conference on Design automation, p.2-7, June 03-07, 1996, Las Vegas, Nevada, United States
	Joel R. Phillips, Projection frameworks for model reduction of weakly nonlinear systems, Proceedings of the 37th conference on Design automation, p.184-189, June 05-09, 2000, Los Angeles, California, United States
	Andrew B. Kahng , Sudhakar Muddu , Egino Sarto, On switch factor based analysis of coupled RC interconnects, Proceedings of the 37th conference on Design automation, p.79-84, June 05-09, 2000, Los Angeles, California, United States
	Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, Practical considerations for passive reduction of RLC circuits, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.214-220, November 07-11, 1999, San Jose, California, United States
	Soha Hassoun, Critical path analysis using a dynamically bounded delay model, Proceedings of the 37th conference on Design automation, p.260-265, June 05-09, 2000, Los Angeles, California, United States
	Nuno Marques , Mattan Kamon , Jacob White , L. Miguel Silveira, A mixed nodal-mesh formulation for efficient extraction and passive reduced-order modeling of 3D interconnects, Proceedings of the 35th annual conference on Design automation, p.297-302, June 15-19, 1998, San Francisco, California, United States
	Paul D. Gross , Ravishankar Arunachalam , Karthik Rajagopal , Lawrence T. Pileggi, Determination of worst-case aggressor alignment for delay calculation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.212-219, November 08-12, 1998, San Jose, California, United States
	Ning Dong , Jaijeet Roychowdhury, Piecewise polynomial nonlinear model reduction, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	M. Kamon , N. Marques , Y. Massoud , L. Silveira , J. White, Interconnect analysis: from 3-D structures to circuit models, Proceedings of the 36th ACM/IEEE conference on Design automation, p.910-914, June 21-25, 1999, New Orleans, Louisiana, United States
	Rony Kay , Lawrence Pileggi, PRIMO: probability interpretation of moments for delay calculation, Proceedings of the 35th annual conference on Design automation, p.463-468, June 15-19, 1998, San Francisco, California, United States
	Lawrence Pileggi, Timing metrics for physical design of deep submicron technologies, Proceedings of the 1998 international symposium on Physical design, p.28-33, April 06-08, 1998, Monterey, California, United States
	H. Levy , W. Scott , D. MacMillen , Jacob White, A rank-one update method for efficient processing of interconnect parasitics in timing analysis, Proceedings of the 37th conference on Design automation, p.75-78, June 05-09, 2000, Los Angeles, California, United States
	Kevin J. Kerns , Andrew T. Yang, Preservation of passivity during RLC network reduction via split congruence transformations, Proceedings of the 34th annual conference on Design automation, p.34-39, June 09-13, 1997, Anaheim, California, United States
	I. M. Elfadel , David D. Ling, A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.66-71, November 09-13, 1997, San Jose, California, United States
	Mattan Kamon , Steve McCormick , Ken Sheperd, Interconnect parasitic extraction in the digital IC design methodology, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.223-231, November 07-11, 1999, San Jose, California, United States
	Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, PRIMA: passive reduced-order interconnect macromodeling algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.58-65, November 09-13, 1997, San Jose, California, United States
	Luca Daniel , Chin Siong Ong , Sok Chay Low , Kwok Hong Lee , Jacob White, Geometrically parameterized interconnect performance models for interconnect synthesis, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Michael W. Beattie , Lawrence T. Pileggi, IC analyses including extracted inductance models, Proceedings of the 36th ACM/IEEE conference on Design automation, p.915-920, June 21-25, 1999, New Orleans, Louisiana, United States
	Youngsoo Shin , Takayasu Sakurai, Estimation of power distribution in VLSI interconnects, Proceedings of the 2001 international symposium on Low power electronics and design, p.370-375, August 2001, Huntington Beach, California, United States
	Yehea I. Ismail, Efficient model order reduction via multi-node moment matching, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.767-774, November 10-14, 2002, San Jose, California
	Anil Samavedam , Karti Mayaram , Terri Fiez, A scalable substrate noise coupling model for mixed-signal ICs, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.128-131, November 07-11, 1999, San Jose, California, United States
	Mike Chou , Jacob White, Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.40-44, November 05-09, 1995, San Jose, California, United States
	Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware interconnect power optimization in domino logic synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.79-89, February 2003
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Sung-Mo Kang, Minimum delay optimization for domino logic circuits---a coupling-aware approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.203-213, April 2003
	Peng Li , Lawrence T. Pileggi, NORM: compact model order reduction of weakly nonlinear systems, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
	Chandramouli V. Kashyap , Byron L. Krauter, A realizable driving point model for on-chip interconnect with inductance, Proceedings of the 37th conference on Design automation, p.190-195, June 05-09, 2000, Los Angeles, California, United States
	Yehea I. Ismail, Improved model-order reduction by using spacial information in moments, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.900-908, October 2003
	Lihong Feng, Parameter independent model order reduction, Mathematics and Computers in Simulation, v.68 n.3, p.221-234, 1 May 2005
	Dian Zhou , Rui-Ming Li, Design and verification of high-speed VLSI physical design, Journal of Computer Science and Technology, v.20 n.2, p.147-165, March 2005
	Peng Li , Weiping Shi, Model order reduction of linear networks with massive ports via frequency-dependent port packing, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Xiaoji Ye , Peng Li , Min Zhao , Rajendran Panda , Jiang Hu, Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	J. Wang , P. Ghanta , S. Vrudhula, Stochastic analysis of interconnect performance in the presence of process variations, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.880-886, November 07-11, 2004
	Bernard N. Sheehan, Projective convolution: RLC model-order reduction using the impulse response, Proceedings of the conference on Design, automation and test in Europe, p.130-es, January 1999, Munich, Germany
	Dinesh Pamunuwa , Shauki Elassaad , Hannu Tenhunen, Analytic Modeling of Interconnects for Deep Sub-Micron Circuits, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.835, November 09-13, 2003
	Sheldon X. -D. Tan, A General S-Domain Hierarchical Network Reduction Algorithm, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.650, November 09-13, 2003
	Joel Phillips , João Afonso , Arlindo Oliveira , L. Miguel Silveira, Analog Macromodeling using Kernel Methods, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.446, November 09-13, 2003
	Peng Li , Xin Li , Yang Xu , Lawrence T. Pileggi, A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.454, November 09-13, 2003
	Peng Li , Frank Liu , Xin Li , Lawrence T. Pileggi , Sani R. Nassif, Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction, Proceedings of the conference on Design, Automation and Test in Europe, p.958-963, March 07-11, 2005
	Lihong Feng , Xuan Zeng , Charles Chiang , Dian Zhou , Qiang Fang, Direct Nonlinear Order Reduction with Variational Analysis, Proceedings of the conference on Design, automation and test in Europe, p.21316, February 16-20, 2004
	Kaveh Shakeri , James D. Meindl, Accelerated modeling of massively coupled RLC interconnects using the relative inductance extraction method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.745-754, June 2008