Delay analysis of the distributed RC line

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Delay analysis of the distributed RC line

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 370 - 375

Year of Publication: 1995

ISBN:0-89791-725-1

Author

Vasant B. Rao

IBM EDA Laboratory, B306/Z3A1, Route 52, Hopewell Junction, NY

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 50, Citation Count: 6

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Andrew B. Kahng , Sudhakar Muddu, Delay analysis of VLSI interconnections using the diffusion equation model, Proceedings of the 31st annual conference on Design automation, p.563-569, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196556]
	2	R. J. Antinone and G. W. Brown, "The Modeling of Resistive Interconnects for Integrated Circuits", IEEE Journal of Solid State Circuits, Vol 18, pp. 200-203, April 1983.
	3	H. B. Bakoglu, Circuits, Interconnects, and Packaging, Addison Wesley, 1990.
	4	M. Healey, Tables of Laplace, Heaviside, Fourier, and Z Transforms, W 8z R Chambers Ltd., 1967.
	5	W. M. Kaufman and S. J. Garrett, "Tapered Distributed Filters", IRE Transactions on Circuit Theory, pp. 329- 336, December 1962.
	6	H. L. Mattes, "Behavior of a Single Transmission Line Stimulated with a Step Function", manuscript, August 1993.
	7	T. Sakurai, "Approximation of Wiring Delay in MOS- FET LSI", IEEE Journal of Solid State Circuits, pp. 418-426, August 1983.
	8	A. Wilnai, "Open-Ended RC Line Model Predicts MOS- FET IC Response", Electron Devices Newsletter, pp. 53- 54, December 15, 1971.
	9	A. B. Kahng and S. Muddu, "A General Methodology for Response and Delay Computations in VLSI Interconnects", technical report UCLA CSD-TR-940015, April 1994.
	10	A. B. Kahng and S. Muddu, "Delay Analysis of VLSI Interconnects Using the Diffusion Equation Model", manuscript submitted to IEEE Trans. on Circuits and Systems, May 1994 (revised February 1995).
	11	Curtis L. Ratzlaff , Nanda Gopal , Lawrence T. Pillage, RICE: Rapid interconnect circuit evaluator, Proceedings of the 28th conference on ACM/IEEE design automation, p.555-560, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127732]
	12	A. B. Kahng and S. Muddu, personal communication, February 1995.

CITED BY 6

	Youxin Gao , D. F. Wong, Shaping a VLSI wire to minimize delay using transmission line model, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.611-616, November 08-12, 1998, San Jose, California, United States
	Andrew B. Kahng , Sudhakar Muddu, Analysis of RC interconnections under ramp input, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.168-192, April 1997
	Keith Nabors , Tze-Ting Fang , Hung-Wen Chang , Kenneth S. Kundert, Lumped interconnect models via Gaussian quadrature, Proceedings of the 34th annual conference on Design automation, p.40-45, June 09-13, 1997, Anaheim, California, United States
	Andrew B. Kahng , Sudhakar Muddu, Analysis of RC interconnections under ramp input, Proceedings of the 33rd annual conference on Design automation, p.533-538, June 03-07, 1996, Las Vegas, Nevada, United States
	Youxin Gao , D. F. Wong, Wire-sizing for delay minimization and ringing control using transmission line model, Proceedings of the conference on Design, automation and test in Europe, p.512-516, March 27-30, 2000, Paris, France
	U. Fassnacht , J. Schietke, Timing analysis and optimization of a high-performance CMOS processor chipset, Proceedings of the conference on Design, automation and test in Europe, p.325-330, February 23-26, 1998, Le Palais des Congrés de Paris, France