The Elmore delay as bound for RC trees with generalized input signals

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The Elmore delay as bound for RC trees with generalized input signals

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 364 - 369

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Rohini Gupta	The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, Texas
Byron Krauter	IBM, Austin, TX
Bogdan Tutuianu	The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, Texas
John Willis	The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, Texas
Lawrence T. Pileggi	The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, Texas

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 37, Citation Count: 23

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Chi-Tsong Chen, Linear System Theory and Design, Saunders College Publishing, Philadelphia, PA, 1984
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	6	W.C. Elmore. The Transient Analysis of Damped Linear Networks with Particular Regard to Wideband Amplifiers. J. Applied Physics, vol. 19(1), 1948.
	7	R. Gupta, B. Tutuianu and L.T. Pillage. The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. Submitted for publication in the IEEE Transactions on CAD. (Available at WWW site: http:/ /artemis.ece.utexas.edu).
	8	M.A. Horowitz. Timing Models for MOS Circuits. Ph.D. thesis, Stanford University, January 1984.
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	17	E.N. Protonotarios and O. Wing. Theory of Nonuniform RC Lines. Part II: Analytic Properties in the Time Domain. IEEE Transactions on Circuit Theory, March 1967.
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CITED BY 23

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	Minghorng Lai , D. F. Wong, Maze routing with buffer insertion and wiresizing, Proceedings of the 37th conference on Design automation, p.374-378, June 05-09, 2000, Los Angeles, California, United States
	Jinan Lou , Amir H. Salek , Massoud Pedram, An exact solution to simultaneous technology mapping and linear placement problem, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.671-675, November 09-13, 1997, San Jose, California, United States
	Bernard N. Sheehan, Predicting coupled noise in RC circuits, Proceedings of the conference on Design, automation and test in Europe, p.517-521, March 27-30, 2000, Paris, France
	Byron Krauter , Rohini Gupta , John Willis , Lawrence T. Pileggi, Transmission line synthesis, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.358-363, June 12-16, 1995, San Francisco, California, United States
	Bogdan Tutuianu , Florentin Dartu , Lawrence Pileggi, An explicit RC-circuit delay approximation based on the first three moments of the impulse response, Proceedings of the 33rd annual conference on Design automation, p.611-616, June 03-07, 1996, Las Vegas, Nevada, United States
	Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Buffer insertion with accurate gate and interconnect delay computation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.479-484, June 21-25, 1999, New Orleans, Louisiana, United States
	Jiang Hu , Sachin S. Sapatnekar, FAR-DS: full-plane AWE routing with driver sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.84-89, June 21-25, 1999, New Orleans, Louisiana, United States
	Xiaodong Yang , Walter H. Ku , Chung-Kuan Cheng, RLC interconnect delay estimation via moments of amplitude and phase response, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.208-213, November 07-11, 1999, San Jose, California, United States
	Lawrence Pileggi, Timing metrics for physical design of deep submicron technologies, Proceedings of the 1998 international symposium on Physical design, p.28-33, April 06-08, 1998, Monterey, California, United States
	Noel Menezes , Ross Baldick , Lawrence T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.144-151, November 05-09, 1995, San Jose, California, United States
	Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
	Bernard N. Sheehan, Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments, Proceedings of the 37th conference on Design automation, p.532-535, June 05-09, 2000, Los Angeles, California, United States
	Andrew B. Kahng , Kei Masuko , Sudhakar Muddu, Analytical delay models for VLSI interconnects under ramp input, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.30-36, November 10-14, 1996, San Jose, California, United States
	Lawrence Pileggi, Coping with RC(L) interconnect design headaches, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.246-253, November 05-09, 1995, San Jose, California, United States
	Jingyu Xu , Xianlong Hong , Tong Jing , Yici Cai , Jun Gu, An efficient hierarchical timing-driven Steiner tree algorithm for global routing, Integration, the VLSI Journal, v.35 n.2, p.69-84, August 2003
	Jiang Hu , Sachin S. Sapatnekar, Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model, Proceedings of the 1999 international symposium on Physical design, p.133-138, April 12-14, 1999, Monterey, California, United States
	Arif Ishaq Abou-Seido , Brian Nowak , Chris Chu, Fitted Elmore delay: a simple and accurate interconnect delay model, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.691-696, July 2004
	Andrew B. Kahng , Bao Liu , Sheldon X.-D. Tan, Efficient decoupling capacitor planning via convex programming methods, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Bao Liu , Sheldon X.-D. Tan, Minimum decoupling capacitor insertion in VLSI power/ground supply networks by semidefinite and linear programs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.11, p.1284-1287, November 2007
	W.-C. D. Lam , J. Jam , C.-K. Koh , V. Balakrishnan , Y. Chen, Statistical based link insertion for robust clock network design, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.588-591, November 06-10, 2005, San Jose, CA
	V. Chandramouli , Karem A. Sakallah, Selection of Voltage Thresholds for Delay Measurement, Analog Integrated Circuits and Signal Processing, v.14 n.1-2, p.9-28, Sept. 1997
	Jingyu Xu , Xianlong Hong , Tong Jing , Yici Cai , Jun Gu, An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.473, January 07-11, 2002