Analysis of switch-level faults by symbolic simulation

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Analysis of switch-level faults by symbolic simulation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 352 - 357

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Lluís Ribas-Xirgo	Centre Nacional de Microelectrònica, CNM (CSIC), Universitat Autònoma de Barcelona, UAB, Campus UAB, 08193 Bellaterra, Barcelona, Spain
Jordi Carrabina-Bordoll	Centre Nacional de Microelectrònica, CNM (CSIC), Universitat Autònoma de Barcelona, UAB, Campus UAB, 08193 Bellaterra, Barcelona, Spain

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 2

	L. Ribas-Xirgo , J. Carrabina-Bordoll, On the reuse of symbolic simulation results for incremental equivalence verification of switch-level circuits, Proceedings of the conference on Design, automation and test in Europe, p.624-631, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Lluís Ribas Xirgo , Jordi Carrabina Bordoll, Digital MOS circuit partitioning with symbolic modeling, Proceedings of the conference on Design, automation and test in Europe, p.103-es, January 1999, Munich, Germany