The validity of retiming sequential circuits

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The validity of retiming sequential circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 316 - 321

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Vigyan Singhal	Department of EECS, University of California at Berkeley, Berkeley, CA
Carl Pixley	Motorola Inc., Bridgepoint Plaza I, 5918 W. Courtyard Dr., Suite 200, Austin, TX
Richard L. Rudell	Synopsys Inc., 700 East Middlefield Road, Mountain View, CA
Robert K. Brayton	Department of EECS, University of California at Berkeley, Berkeley, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 14

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K.-T. Cheng. Redundancy Removal for Sequential Circuits Without Reset States. IEEE Transactions on Computer-Aided Design of lntegrated Circuits, 12(1):13-24, January 1993.
	2	E. B. Eichelberger. Hazard Detection in Combinational and Sequential Circuits. IBM J. Res. and Devep., pages 90-99, March 1965.
	3	J. S. Jephson, R. R McQuarrie, and R. E. Vogelsberg. A Three- Value Computer Design Verification System. IBM J. Res. and Devep., pages 178-188, 1969.
	4	C. E. Leiserson and J. B. Saxe. Optimizing Synchronous Systems. Journal of VLSI and Computer Systems, 1(1):41-67, Spring 1983.
	5	T. E. Marchok, A. E1-Maleh, W. Maly, and J. Rajski. Test Set Preservation under Retiming Transformation. Technical Report CMUCAD-94-23, Carnegie Mellon University, 1994. Presented at Intl. Test Synthesis Workshop, Santa Barbara, CA, May 1994.
	6	C. Pixley. A Theory and Implementation of Sequential Hardware Equivalence. IEEE Transactions on Computer-Aided Design of Inwgrawd Circuits, 11 (12): 1469-1494, December 1992.
	7	Carl Pixley , Vigyan Singhal , Adnan Aziz , Robert K. Brayton, Multi-level synthesis for safe replaceability, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.442-449, November 06-10, 1994, San Jose, California, United States
	8	I. Pomeranz , S. M. Reddy, Classification of Faults in Synchronous Sequential Circuits, IEEE Transactions on Computers, v.42 n.9, p.1066-1077, September 1993 [doi>10.1109/12.241596]
	9	Narendra Shenoy , Richard Rudell, Efficient implementation of retiming, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.226-233, November 06-10, 1994, San Jose, California, United States
	10	H. J. Touati and R. K. Brayton. Computing the Initial States of Retimed Circuits. IEEE Transactions on Computer-Aided Design of lntegrated Circuits, 12(1):157-162, January 1993.

CITED BY 14

	Rajeev K. Ranjan , Vigyan Singhal , Fabio Somenzi , Robert K. Brayton, On the optimization power of retiming and resynthesis transformations, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.402-407, November 08-12, 1998, San Jose, California, United States
	Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen, Verifying sequential equivalence using ATPG techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.244-275, April 2001
	Mahesh A. Iyer , David E. Long , Miron Abramovici, Identifying sequential redundancies without search, Proceedings of the 33rd annual conference on Design automation, p.457-462, June 03-07, 1996, Las Vegas, Nevada, United States
	Soha Hassoun , Tiziano Villa, Optimization of synchronous circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Vigyan Singhal , Carl Pixley , Adnan Aziz , Robert K. Brayton, Exploiting power-up delay for sequential optimization, Proceedings of the conference on European design automation, p.54-59, September 18-22, 1995, Brighton, England
	Surendra Bommu , Niall O'Neill , Maciej Ciesielski, Retiming-based factorization for sequential logic optimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.373-398, July 2000
	Shi-Yu Huang, On speeding up extended finite state machines using catalyst circuitry, Proceedings of the 2001 conference on Asia South Pacific design automation, p.583-588, January 2001, Yokohama, Japan
	Maher N. Mneimneh , Karem A. Sakallah , John Moondanos, Preserving synchronizing sequences of sequential circuits after retiming, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.579-584, January 27-30, 2004, Yokohama, Japan
	Thomas E. Marchok , Aiman El-Maleh , Janusz Rajski , Wojciech Maly, Testability Implications of Performance-Driven Logic Synthesis, IEEE Design & Test, v.12 n.2, p.32-39, June 1995
	G. Hasteer , A. Mathur , P. Bannerjee, Efficient equivalence checking of multi-phase designs using phase abstraction and retiming, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.4, p.600-625, Oct. 1998
	Hiroyuki Yotsuyanagi , Seiji Kajihara , Kozo Kinoshita, Synthesis of Sequential Circuits by Redundancy Removal and Retiming, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.81-92, Aug. 1997
	Rajeev K. Ranjan , Vigyan Singhal , Fabio Somenzi , Robert K. Brayton, Using combinational verification for sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.32-es, January 1999, Munich, Germany
	Priyank Kalla , Maciej J. Ciesielski, Performance driven resynthesis by exploiting retiming-induced state register equivalence, Proceedings of the conference on Design, automation and test in Europe, p.125-es, January 1999, Munich, Germany
	Hai Zhou, A new efficient retiming algorithm derived by formal manipulation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-19, January 2008