A fresh look at retiming via clock skew optimization

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A fresh look at retiming via clock skew optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 310 - 315

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Rahul B. Deokar	Department of Electrical and Computer Engineering, 201 Coover Hall, Iowa State University, Ames, IA
Sachin S. Sapatnekar	Department of Electrical and Computer Engineering, 201 Coover Hall, Iowa State University, Ames, IA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 16, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. E. Leiserson and J. B. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5-35, 1991.
	2	John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
	3	H.-G. Martin, "Retiming by combination of relocation and clock delay adjustment," in Proceedings of the European Design Automation Conference, pp. 384-389, 1993.
	4	B. Lockyear and C. Ebeling, "Minimizing the effect of clock skew via circuit retiming," Tech. Rep. UW- CSE-93-05-04, Department of Computer Science and Engineering, University of Washington, Seattle, 1993.
	5	L.-F. Chao and E. H.-M. Sha, "Retiming and clock skew for synchronous systems," in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.283-1.286, 1994.
	6	R. B. Deokar and S. S. Sapatnekar, "A graphtheoretic approach to clock skew optimization," in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.407-1.410, 1994.
	7	Narendra Shenoy , Richard Rudell, Efficient implementation of retiming, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.226-233, November 06-10, 1994, San Jose, California, United States
	8	R.-S. Tsay, "An exact zero-skew clock routing algorithm," IEEE Transactions on Computer-Aided Design, vol. 12, pp. 242-249, Feb. 1993.
	9	S. S. Sapatnekar and R. B. Deokar, "Utilizing the retiming-skew equivalence in an efficient algorithm for retiming large circuits," Tech. Rep. ISU-CPRE- 94-SS06, Iowa State University, Ames, IA, 1994.
	10	D. Joy and M. Ciesielski, "Clock period minimization with wave pipelining," IEEE Transactions on Computer-Aided Design, vol. 12, pp. 461-472, Apr. 1993.
	11	Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Minimum padding to satisfy short path constraints, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.156-161, November 07-11, 1993, Santa Clara, California, United States
	12	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	13	Shimon Even, Graph Algorithms, W. H. Freeman & Co., New York, NY, 1979
	14	H. J. Touati and R. K. Brayton, "Computing the initial states of retimed circuits," IEEE Transactions on Computer-Aided Design, vol. 12, pp. 157-162, Jan. 1993.

CITED BY 7

	François R. Boyer , El Mostapha Aboulhamid , Yvon Savaria , Michel Boyer, Optimal design of synchronous circuits using software pipelining techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.4, p.516-532, October 2001
	Abdallah Tabbara , Robert K. Brayton , A. Richard Newton, Retiming for DSM with area-delay trade-offs and delay constraints, Proceedings of the 36th ACM/IEEE conference on Design automation, p.725-730, June 21-25, 1999, New Orleans, Louisiana, United States
	Naresh Maheshwari , Sachin S. Sapatnekar, An improved algorithm for minimum-area retiming, Proceedings of the 34th annual conference on Design automation, p.2-7, June 09-13, 1997, Anaheim, California, United States
	Zongwei Lu , Zhenghui Lin , Houpeng Chen, Variables bounding based retiming algorithm, Journal of Computer Science and Technology, v.17 n.6, p.797-806, November 2002
	Noureddine Chabini , El Mostapha Aboulhamid , Ismaïl Chabini , Yvon Savaria, Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.187-204, April 2005
	Chuan Lin , Hai Zhou, Optimal wire retiming without binary search, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.452-458, November 07-11, 2004
	Chris Chu , Evangeline F. Y. Young , Dennis K. Y. Tong , Sampath Dechu, Retiming with Interconnect and Gate Delay, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.221, November 09-13, 2003