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DELAY: an efficient tool for retiming with realistic delay modeling

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 304 - 309

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Kumar N. Lalgudi	Department of Electrical Engineering, Yale University, New Haven, CT
Marios C. Papaefthymiou	Department of Electrical Engineering, Yale University, New Haven, CT

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 12, Citation Count: 18

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	6	K. N. Lalgudi , M. C. Papaefthymiou, Efficient retiming under a general delay model, Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95), p.368, March 27-29, 1995
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	15	Marios C. Papaefthymiou , Keith H. Randall, TIM: a timing package for two-phase, level-clocked circuitry, Proceedings of the 30th international conference on Design automation, p.497-502, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164998]
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CITED BY 18

	Xun Liu , Marios C. Papaefthymiou , Eby G. Friedman, Maximizing performance by retiming and clock skew scheduling, Proceedings of the 36th ACM/IEEE conference on Design automation, p.231-236, June 21-25, 1999, New Orleans, Louisiana, United States
	A. Ranjan , A. Srivastava , V. Karnam , M. Sarrafzadeh, Layout aware retiming, Proceedings of the 11th Great Lakes symposium on VLSI, p.25-30, March 2001, West Lafayette, Indiana, United States
	Kumar N. Lalgudi , Marios C. Papaefthymiou , Miodrag Potkonjak, Optimizing computations for effective block-processing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.604-630, July 2000
	Soha Hassoun , Tiziano Villa, Optimization of synchronous circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Surendra Bommu , Niall O'Neill , Maciej Ciesielski, Retiming-based factorization for sequential logic optimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.373-398, July 2000
	Ingmar Neumann , Wolfgang Kunz, Placement driven retiming with a coupled edge timing model, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Naresh Maheshwari , Sachin S. Sapatnekar, An improved algorithm for minimum-area retiming, Proceedings of the 34th annual conference on Design automation, p.2-7, June 09-13, 1997, Anaheim, California, United States
	Kumar N. Lalgudi , Marios C. Papaefthymiou , Miodrag Potkonjak, Optimizing systems for effective block-processing: the k-delay problem, Proceedings of the 33rd annual conference on Design automation, p.714-719, June 03-07, 1996, Las Vegas, Nevada, United States
	Zongwei Lu , Zhenghui Lin , Houpeng Chen, Variables bounding based retiming algorithm, Journal of Computer Science and Technology, v.17 n.6, p.797-806, November 2002
	Sissades Tongsima , Timothy W. O'neil , Chantana Chantrapornchai , Edwin H.-M. Sha, Properties and Algorithms for Unfolding of Probabilistic Data-Flow Graphs, Journal of VLSI Signal Processing Systems, v.25 n.3, p.215-233, July 2000
	Peter Suaris , Dongsheng Wang , Nan-Chi Chou, A practical cut-based physical retiming algorithm for field programmable gate arrays, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Chuan Lin , Hai Zhou, An efficient retiming algorithm under setup and hold constraints, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Chuan Lin , Hai Zhou, Optimal wire retiming without binary search, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.452-458, November 07-11, 2004
	Priyank Kalla , Maciej J. Ciesielski, Performance driven resynthesis by exploiting retiming-induced state register equivalence, Proceedings of the conference on Design, automation and test in Europe, p.125-es, January 1999, Munich, Germany
	Xun Liu , Marios C. Papaefthymiou , Eby G. Friedman, Minimizing sensitivity to delay variations in high-performance synchronous circuits, Proceedings of the conference on Design, automation and test in Europe, p.126-es, January 1999, Munich, Germany
	Chris Chu , Evangeline F. Y. Young , Dennis K. Y. Tong , Sampath Dechu, Retiming with Interconnect and Gate Delay, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.221, November 09-13, 2003
	Ulrich Seidl , Klaus Eckl , Frank Johannes, Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information, Proceedings of the conference on Design, Automation and Test in Europe, p.10770, March 03-07, 2003
	Chuan Lin , Hai Zhou, Wire Retiming for System-on-Chip by Fixpoint Computation, Proceedings of the conference on Design, automation and test in Europe, p.21092, February 16-20, 2004