Timed shared circuits

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Timed shared circuits: a power-efficient design style and synthesis tool

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 254 - 260

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Luciano Lavagno	Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CA
Patrick C. McGeer	Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CA
Alexander Saldanha	Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CA
Alberto L. Sangiovanni-Vincentelli	Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
	2	D. A. Huffman. A method for the construction of minimum redundancy codes. In Proceedings of the IRE, volume 40, pages 1098-1101, September, 1952.
	3	R. Murgai, R.K. Brayton, and A.L. Sangiovanni-Vincentelli. Decomposition for minimum transition activity. In Proceedings of the Low-Power Workshop, Napa, April 1994.

CITED BY 13

	Rolf Drechsler , Nicole Drechsler , Wolfgang Günther, Fast exact minimization of BDDs, Proceedings of the 35th annual conference on Design automation, p.200-205, June 15-19, 1998, San Francisco, California, United States
	Per Lindgren , Mikael Kerttu , Mitch Thornton , Rolf Drechsler, Low power optimization technique for BDD mapped circuits, Proceedings of the 2001 conference on Asia South Pacific design automation, p.615-621, January 2001, Yokohama, Japan
	Arlindo L. Oliveira , Luca P. Carloni , Tiziano Villa , Alberto L. Sangiovanni-Vincentelli, Exact Minimization of Binary Decision Diagrams Using Implicit Techniques, IEEE Transactions on Computers, v.47 n.11, p.1282-1296, November 1998
	Youpyo Hong , Peter A. Beerel , Jerry R. Burch , Kenneth L. McMillan, Safe BDD minimization using don't cares, Proceedings of the 34th annual conference on Design automation, p.208-213, June 09-13, 1997, Anaheim, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Wolfgang Günther , Rolf Drechsler, Minimization of free BDDs, Integration, the VLSI Journal, v.32 n.1-3, p.41-59, November 2002
	Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States
	Swarup Bhunia , Nilanjan Banerjee , Qikai Chen , Hamid Mahmoodi , Kaushik Roy, A novel synthesis approach for active leakage power reduction using dynamic supply gating, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Nilanjan Banerjee , Kaushik Roy , Hamid Mahmoodi , Swarup Bhunia, Low power synthesis of dynamic logic circuits using fine-grained clock gating, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Swaroop Ghosh , Swarup Bhunia , Kaushik Roy, Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Swaroop Ghosh , Swarup Bhunia , Kaushik Roy, Low-Power and testable circuit synthesis using Shannon decomposition, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.4, p.47-es, September 2007
	Swaroop Ghosh , Swarup Bhunia , Kaushik Roy, A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	L. Benini , G. De Micheli , A. Macii , E. Macii , M. Poncino , R. Scarsi, Glitch power minimization by gate freezing, Proceedings of the conference on Design, automation and test in Europe, p.36-es, January 1999, Munich, Germany