Logic extraction and factorization for low power

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Logic extraction and factorization for low power

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 248 - 253

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Sasan Iman	Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
Massoud Pedram	Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 20, Citation Count: 19

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
	2	A. P. Chandrakasan, S. S. Scheng, and R. W. Broderson. Low power CMOS digital design. IEEE Journal of Solid State Circuits, 27(4):473-483, April 1992.
	3	Sasan Iman , Massoud Pedram, Multi-level network optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.372-377, November 06-10, 1994, San Jose, California, United States
	4	Radu Marculescu , Diana Marculescu , Massoud Pedram, Switching activity analysis considering spatiotemporal correlations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.294-299, November 06-10, 1994, San Jose, California, United States
	5	R. Brayton, C. McMullen. The decomposition and factorization of boolean expressions. In Proc. Int. Symp. Circ. Sys. (ISCAS- 82)pages 49-54, 1982.
	6	F.N. Najm, R. Burch, P. Yang, I. Hajj, Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE transactions on CAD, 1990, volume 9, pages 439-450.
	7	Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
	8	K. Roy, S. C.Prasad. Circuit activity based logic synthesis for low power reliable operations. IEEE Transactions on VLSI systems. 1 (4):503-513, December 1993.
	9	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	10	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Technology decomposition and mapping targeting low power dissipation, Proceedings of the 30th international conference on Design automation, p.68-73, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164577]
	11	H. Vaishnav, M. Pedram, PCUBE: A performance driven placement algorithm for low power designs, EuroDac, Sept. 1993, pages 72-77.
	12	Albert Ren Rui Wang, Algorithms for multilevel logic optimization, University of California at Berkeley, Berkeley, CA, 1991

CITED BY 19

	Sasan Iman , Massoud Pedram, POSE: power optimization and synthesis environment, Proceedings of the 33rd annual conference on Design automation, p.21-26, June 03-07, 1996, Las Vegas, Nevada, United States
	P. Girard , C. Landrault , S. Pravossoudovitch , D. Severac, A gate resizing technique for high reduction in power consumption, Proceedings of the 1997 international symposium on Low power electronics and design, p.281-286, August 18-20, 1997, Monterey, California, United States
	S. Roy , H. Arts , P. Banerjee, PowerShake: a low power driven clustering and factoring methodology for Boolean expressions, Proceedings of the conference on Design, automation and test in Europe, p.967-968, February 23-26, 1998, Le Palais des Congrés de Paris, France
	C. Lennard , P. Buch , A. Newton, Logic synthesis using power-sensitive don't care sets, Proceedings of the 1996 international symposium on Low power electronics and design, p.293-296, August 12-14, 1996, Monterey, California, United States
	Sumit Roy , Harm Arts , Prithviraj Banerjee, PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.601-606, November 08-12, 1998, San Jose, California, United States
	Luca P. Carloni , Patrick C. McGeer , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli, Trace driven logic synthesis—application to power minimization, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.581-588, November 09-13, 1997, San Jose, California, United States
	Olivier Coudert , Ramsey Haddad, Integrated resynthesis for low power, Proceedings of the 1996 international symposium on Low power electronics and design, p.169-174, August 12-14, 1996, Monterey, California, United States
	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	P. Vuillod , L. Benini , G. De Micheli, Re-mapping for low power under tight timing constraints, Proceedings of the 1997 international symposium on Low power electronics and design, p.287-292, August 18-20, 1997, Monterey, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Bernhard Rohfleisch , Alfred Kölbl , Bernd Wurth, Reducing power dissipation after technology mapping by structural transformations, Proceedings of the 33rd annual conference on Design automation, p.789-794, June 03-07, 1996, Las Vegas, Nevada, United States
	Glenn Holt , Akhilesh Tyagi, Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis, Proceedings of the 1997 international symposium on Physical design, p.48-53, April 14-16, 1997, Napa Valley, California, United States
	M. Koegst , K. Feske , G. Franke, State assignment for FSM low power design, Proceedings of the conference on European design automation, p.28-33, September 1996, Geneva, Switzerland
	S. Gavrilov , A. Glebov , S. Pullela , S. C. Moore , A. Dharchoudhury , R. Panda , G. Vijayan , D. T. Blaauw, Library-less synthesis for static CMOS combinational logic circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.658-662, November 09-13, 1997, San Jose, California, United States
	Surendra Bommu , Niall O'Neill , Maciej Ciesielski, Retiming-based factorization for sequential logic optimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.373-398, July 2000
	Steven M. Nowick , Michael Theobald, Synthesis of low-power asynchronous circuits in a specified environment, Proceedings of the 1997 international symposium on Low power electronics and design, p.92-95, August 18-20, 1997, Monterey, California, United States
	Rajendran Panda , Farid N. Najm, Technology-dependent transformations for low-power synthesis, Proceedings of the 34th annual conference on Design automation, p.650-655, June 09-13, 1997, Anaheim, California, United States
	N. Julien , S. Gailhard , E. Martin, Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT, Journal of VLSI Signal Processing Systems, v.35 n.2, p.195-211, September 2003
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998