A survey of optimization techniques targeting low power VLSI circuits

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A survey of optimization techniques targeting low power VLSI circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 242 - 247

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Srinivas Devadas	Massachusetts Institute of Technology, Department of EECS
Sharad Malik	Princeton University, Department of EE

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 24, Downloads (12 Months): 158, Citation Count: 29

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 29

	Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin , Rita Chen , Debashree Ghosh, Techniques for low energy software, Proceedings of the 1997 international symposium on Low power electronics and design, p.72-75, August 18-20, 1997, Monterey, California, United States
	Per Lindgren , Mikael Kerttu , Mitch Thornton , Rolf Drechsler, Low power optimization technique for BDD mapped circuits, Proceedings of the 2001 conference on Asia South Pacific design automation, p.615-621, January 2001, Yokohama, Japan
	Xiangfeng Chen , Peicheng Pen , C. L. Liu, Desensitization for power reduction in sequential circuits, Proceedings of the 33rd annual conference on Design automation, p.795-800, June 03-07, 1996, Las Vegas, Nevada, United States
	Chi-Hong Hwang , Allen C.-H. Wu, A predictive system shutdown method for energy saving of event-driven computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.226-241, April 2000
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	R. Llopis , M. Sachdev, Low power, testable dual edge triggered flip-flops, Proceedings of the 1996 international symposium on Low power electronics and design, p.341-345, August 12-14, 1996, Monterey, California, United States
	M. Koegst , K. Feske , G. Franke, State assignment for FSM low power design, Proceedings of the conference on European design automation, p.28-33, September 1996, Geneva, Switzerland
	Marcus T. Schmitz , Bashir M. Al-Hashimi, Considering power variations of DVS processing elements for energy minimisation in distributed systems, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Chi-Hong Hwang , Allen C.-H. Wu, A predictive system shutdown method for energy saving of event-driven computation, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.28-32, November 09-13, 1997, San Jose, California, United States
	Steven M. Nowick , Michael Theobald, Synthesis of low-power asynchronous circuits in a specified environment, Proceedings of the 1997 international symposium on Low power electronics and design, p.92-95, August 18-20, 1997, Monterey, California, United States
	P. Girard , C. Landrault , S. Pravossoudovitch , D. Severac, A gate resizing technique for high reduction in power consumption, Proceedings of the 1997 international symposium on Low power electronics and design, p.281-286, August 18-20, 1997, Monterey, California, United States
	Dinesh Ramanathan , Rajesh Gupta, System level online power management algorithms, Proceedings of the conference on Design, automation and test in Europe, p.606-611, March 27-30, 2000, Paris, France
	Yann-Rue Lin , Cheng-Tsung Hwang , Allen C.-H. Wu, Scheduling techniques for variable voltage low power designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.81-97, April 1997
	Jerry Hom , Ulrich Kremer, Energy management of virtual memory on diskless devices, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
	Marcus T. Schmitz , Bashir M. Al-Hashimi , Petru Eles, Iterative schedule optimization for voltage scalable distributed embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.1, p.182-217, February 2004
	Bita Gorjiara , Nader Bagherzadeh , Pai Chou, An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Dinesh Ramanathan , Sandy Irani , Rajesh Gupta, Latency effects of system level power management algorithms, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Bita Gorji-Ara , Pai Chou , Nader Bagherzadeh , Mehrdad Reshadi , David Jensen, Fast and efficient voltage scheduling by evolutionary slack distribution, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.659-662, January 27-30, 2004, Yokohama, Japan
	Radu Muresan , Catherine Gebotys, Instantaneous current modeling in a complex VLIW processor core, ACM Transactions on Embedded Computing Systems (TECS), v.4 n.2, p.415-451, May 2005
	Jens-Peter Kaps , Kaan Yuksel , Berk Sunar, Energy Scalable Universal Hashing, IEEE Transactions on Computers, v.54 n.12, p.1484-1495, December 2005
	Yi-Ping You , Chun-Yen Tseng , Yu-Hui Huang , Po-Chiun Huang , TingTing Hwang , Sheng-Yu Hsu, Low-power techniques for network security processors, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Ahmed M. Shams , Tarek K. Darwish , Magdy A. Bayoumi, Performance analysis of low-power 1-Bit CMOS full adder cells, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.20-29, 2/1/2002
	Yung-Chia Lin , Yi-Ping You , Chung-Wen Huang , Jenq Kuen Lee , Wei-Kuan Shih , Ting-Ting Hwang, Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains, The Journal of Supercomputing, v.42 n.2, p.201-223, November 2007
	Subash Chandar , Mahesh Mehendale , R. Govindarajan, Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding, Journal of VLSI Signal Processing Systems, v.44 n.3, p.245-267, September 2006
	Vinod Viswanath , Jacob A. Abraham , Warren A. Hunt, Jr, Automatic insertion of low power annotations in RTL for pipelined microprocessors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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	Stefan Gerstendörfer , Hans-Joachim Wunderlich, Minimized Power Consumption for Scan-Based BIST, Journal of Electronic Testing: Theory and Applications, v.16 n.3, p.203-212, June 2000
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