Logic verification methodology for PowerPC microprocessors

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Logic verification methodology for PowerPC microprocessors

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 234 - 240

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Charles H. Malley	Motorola Inc., 9737 Great Hills Trail, Austin, Texas
Max Dieudonné	IBM Corporation, 11400 Burnet Road, Austin, Texas

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	11	T. Sasaki, S. Kato, N. Nomizu, and H. Tanaka, "Logic Design Verification Using Automated Test Generation," Proc. 1984 International Test Conference, pp. 99-94, 1984.
	12	Timothy J. Barnes, SKILL: A CAD system extension language, Proceedings of the 27th ACM/IEEE conference on Design automation, p.266-271, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123271]
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CITED BY 8

	Li-C. Wang , Magdy S. Abadir, Experience in Validation of PowerPCTM Microprocessor Embedded Arrays, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.191-205, August-October 1999
	Li-C. Wang , Magdy S. Abadir , Nari Krishnamurthy, Automatic generation of assertions for formal verification of PowerPC microprocessor arrays using symbolic trajectory evaluation, Proceedings of the 35th annual conference on Design automation, p.534-537, June 15-19, 1998, San Francisco, California, United States
	Li-C. Wang , Magdy S. Abadir , Jing Zeng, On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.4, p.524-532, Oct. 1998
	L.-C. Wang , M. S. Abadir , J. Zeng, Measuring the effectiveness of various design validation approaches for PowerPCTM microprocessor arrays, Proceedings of the conference on Design, automation and test in Europe, p.273-277, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Françoise Casaubieilh , Anthony McIsaac , Mike Benjamin , Mike Bartley , François Pogodalla , Frédéric Rocheteau , Mohamed Belhadj , Jeremy Eggleton , Gérard Mas , Geoff Barrett , Christian Berthet, Functional verification methodology of Chameleon processor, Proceedings of the 33rd annual conference on Design automation, p.421-426, June 03-07, 1996, Las Vegas, Nevada, United States
	Jaehong Park , Carl Pixley , Michael Burns , Hyunwoo Cho, An Efficient Logic Equivalence Checker for Industrial Circuits, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.91-106, Feb/April 2000
	Li-C. Wang , Magdy S. Abadir, On Efficiently Producing Quality Tests forCustom Circuits in PowerPC™ Microprocessors, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.121-130, Feb/April 2000
	Li-C. Wang , Magdy S. Abadir, Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.121-135, Oct. 1998