Digital receiver design using VHDL generation from data flow graphs

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Digital receiver design using VHDL generation from data flow graphs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 228 - 233

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Peter Zepter	Integrated Systems for Signal Processing, Aachen University of Technology, Templergraben 55, D-52056 Aachen, Germany
Thorsten Grötker	Integrated Systems for Signal Processing, Aachen University of Technology, Templergraben 55, D-52056 Aachen, Germany
Heinrich Meyr	Integrated Systems for Signal Processing, Aachen University of Technology, Templergraben 55, D-52056 Aachen, Germany

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 24, Citation Count: 11

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Glenn Jennings, A case against event-driven simulation for digital system design, Proceedings of the 24th annual symposium on Simulation, p.170-176, April 1991, New Orleans, Louisiana, United States
	2	O.J. Joeressen, G. Schneider, and H. Meyr, "Systematic Design Optimization of a Competitive Soft-Concatenated Decoding System," in VLSI Signal Processing 6 (L. Eggermont et al., ed.), pp. 105-113, IEEE, 1993.
	3	Cadence Design Systems, 919 E. Hillsdale Blvd., Foster City, CA 94404, USA, SPW User's Manual.
	4	P.B. Tjahjadi, P. T. Yang, B. C. Wong, B.-Y. Chung, E. G. Cohen, and R. Jain, "Vanda- a CAD system for communication signal processing circuits design," in VLSI Signal Processing IV, ch. 5, IEEE Press, 1990.
	5	Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA 94043, USA, COSSAP User's Manual.
	6	E. A. Lee, Consistency in Dataflow Graphs, IEEE Transactions on Parallel and Distributed Systems, v.2 n.2, p.223-235, April 1991 [doi>10.1109/71.89067]
	7	J.T. Buck and E. A. Lee, "Scheduling dynamic dataflow graphs with bounded memory using the token flow model," in Proc. ICASSP'93, pp. 1-429-I-432, IEEE, 1993.
	8	T. Murata, "Petri nets: Properties, analysis and applications," Proc. of the IEEE, vol. 77, pp. 541-580, April 1989.
	9	Edward Ashford Lee , David G. Messerschmitt, Static scheduling of synchronous data flow programs for digital signal processing, IEEE Transactions on Computers, v.36 n.1, p.24-35, Jan. 1987 [doi>10.1109/TC.1987.5009446]
	10	H. V. Jagadisch and T. Kailath, "Obtaining schedules for digital systems," IEEE Trans. on Signal Processing, vol. 39, pp. 2296- 2316, Oct. 1991.
	11	C. E. Leiserson, F. Rose, and J. Saxe, "Optimizing synchronous circuitry for retiming," in Proc. of the 3rd CaItech Conf. on VLSI, (Pasadena), pp. 87-116, March 1983.
	12	U. Lambrette and H. Meyr, "Two timing recovery algorithms for MSK," in Intl. Conf. on Comm., 1994.
	13	Texas Instruments, FPGA Data Manual.

CITED BY 11

	Chanik Park , Soonhoi Ha, Hardware synthesis from SPDF representation for multimedia applications, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Jens Horstmannshoff , Heinrich Meyr, Efficient building block based RTL code generation from synchronous data flow graphs, Proceedings of the 37th conference on Design automation, p.552-555, June 05-09, 2000, Los Angeles, California, United States
	Chanik Park , Sungchan Kim , Soonhoi Ha, A dataflow specification for system level synthesis of 3D graphics applications, Proceedings of the 2001 conference on Asia South Pacific design automation, p.78-84, January 2001, Yokohama, Japan
	H. Keding , M. Willems , M. Coors , H. Meyr, FRIDGE: a fixed-point design and simulation environment, Proceedings of the conference on Design, automation and test in Europe, p.429-435, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Markus Willems , Volker Bürsgens , Holger Keding , Thorsten Grötker , Heinrich Meyr, System level fixed-point design based on an interpolative approach, Proceedings of the 34th annual conference on Design automation, p.293-298, June 09-13, 1997, Anaheim, California, United States
	Hyunuk Jung , Kangnyoung Lee , Soonhoi Ha, Efficient hardware controller synthesis for synchronous dataflow graph in system level design, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Hyunuk Jung , Soonhoi Ha, Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
	Hyunuk Jung , Kangnyoung Lee , Soonhoi Ha, Efficient hardware controller synthesis for synchronous dataflow graph in system level design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.423-428, August 2002
	T. Grotker , R. Schoenen , H. Meyr, PCC: a modeling technique for mixed control/data flow systems, Proceedings of the 1997 European conference on Design and Test, p.482, March 17-20, 1997
	Jens Horstmannshoff , Heinrich Meyr, Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs, Proceedings of the 12th international symposium on System synthesis, p.38, November 01-04, 1999
	Hyunuk Jung , Hoeseok Yang , Soonhoi Ha, Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis, Journal of Signal Processing Systems, v.52 n.1, p.13-34, July 2008