Multi-way partitioning for minimum delay for look-up table based FPGAs

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Multi-way partitioning for minimum delay for look-up table based FPGAs

Full text

Pdf (103 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 201 - 210

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Prashant Sawkar	Electrical and Computer Engineering Dept., Carnegie-Mellon University, Pittsburgh, PA
Donald Thomas	Electrical and Computer Engineering Dept., Carnegie-Mellon University, Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 11

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/217474.217530 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Roman Kužnar , Franc Brglez , Krzysztof Kozminski, Cost minimization of partitions into multiple devices, Proceedings of the 30th international conference on Design automation, p.315-320, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164910]
	2	Roman Kužnar , Franc Brglez , Baldomir Zajc, Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect, Proceedings of the 31st annual conference on Design automation, p.238-243, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196364]
	3	Kalapi Roy , Carl Sechen, A timing driven N-way chip and multi-chip partitioner, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.240-247, November 07-11, 1993, Santa Clara, California, United States
	4	V. Chvatal, "A Greedy Heuristic For the Set-Covering Problem," Mathematics of Operations Research, 4(3), pp 233- 235, 1979.
	5	Prashant Srinivas Sawkar, Performance optimized partitioning and technology mapping for FPGAs, Carnegie Mellon University, Pittsburgh, PA, 1995

CITED BY 11

	Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Timing-driven placement for hierarchical programmable logic devices, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.3-11, February 2001, Monterey, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Performance-driven multi-FPGA partitioning using functional clustering and replication, Proceedings of the 35th annual conference on Design automation, p.283-286, June 15-19, 1998, San Francisco, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.638-643, November 10-14, 1996, San Jose, California, United States
	S. A. Senouci , A. Amoura , H. Krupnova , G. Saucier, Timing driven floorplanning on programmable hierarchical targets, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.85-92, February 22-25, 1998, Monterey, California, United States
	Ranga Vemuri , Sriram Govindarajan , Iyad Ouaiss , Meenakshi Kaul , Vinoo Srinivasan , Shankar Radhakrishnan , Sujatha Sundaraman , Satish Ganesan , Awartika Pandey , Preetham Lakshmikanthan, Automated design synthesis and partitioning for adaptive reconfigurable hardware, Hardware implementation of intelligent systems, Physica-Verlag GmbH, Heidelberg, Germany, 2001
	Frank Vahid, I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.27-34, February 09-11, 1997, Monterey, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Multiway FPGA partitioning by fully exploiting design hierarchy, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.1, p.34-50, Jan. 2000
	Frank M. Johannes, Partitioning of VLSI circuits and systems, Proceedings of the 33rd annual conference on Design automation, p.83-87, June 03-07, 1996, Las Vegas, Nevada, United States
	Young-Su Kwon , Chong-Min Kyung, ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.7, p.861-864, July 2005
	O. Coudert, Solving Graph Optimization Problems with ZBDDs, Proceedings of the 1997 European conference on Design and Test, p.224, March 17-20, 1997