Combining deterministic and genetic approaches for sequential circuit test generation

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Combining deterministic and genetic approaches for sequential circuit test generation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 183 - 188

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Elizabeth M. Rudnick	Motorola, Incorporated, Austin, TX
Janak H. Patel	Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 15

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	14	V. D. Agrawal, K. T. Cheng, and P. Agrawal, "A directed search method for test generation using a concurrent simulator," IEEE Trans. Computer-Aided Design, vol. 8, no. 2, pp. 131-138, February 1989.
	15	Daniel G. Saab , Youssef G. Saab , Jacob A. Abraham, CRIS: a test cultivation program for sequential VLSI circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.216-219, November 1992, Santa Clara, California, United States
	16	M. Srinivas and L. M. Patnaik, "A simulation-based test generation scheme using genetic algorithms," Proc. Int. Conf. VLSI Design, pp. 132-135, 1993.
	17	E. M. Rudnick, J. G. Holm, D. G. Saab, and J. H. Patel, "Application of simple genetic algorithms to sequential circuit test generation," Proc. European Design and Test Conf., pp. 40-45, 1994.
	18	Elizabeth M. Rudnick , Janak H. Patel , Gary S. Greenstein , Thomas M. Niermann, Sequential circuit test generation in a genetic algorithm framework, Proceedings of the 31st annual conference on Design automation, p.698-704, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196619]
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CITED BY 15

	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Dynamic state traversal for sequential circuit test generation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.548-565, July 2000
	Kwang-Ting Cheng, Gate-level test generation for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.405-442, Oct. 1996
	Boris Ratchev , Mike Hutton , Gregg Baeckler , Babette van Antwerpen, Verifying the correctness of FPGA logic synthesis algorithms, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Ismed Hartanto , Vamsi Boppana , W. Kent Fuchs, Identification of unsettable flip-flops for partial scan and faster ATPG, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.63-66, November 10-14, 1996, San Jose, California, United States
	Xijiang Lin , Irith Pomeranz , Sudhakar M. Reddy, Techniques for improving the efficiency of sequential circuit test generation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.147-151, November 07-11, 1999, San Jose, California, United States
	Ilker Hamzaoglu , Janak H. Patel, Deterministic test pattern generation techniques for sequential circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Irith Pomeranz , Sudhakar M. Reddy, Simulation based test generation for scan designs, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Irith Pomeranz , Sudhakar M. Reddy, A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n$n$-Detections in Combinational Circuits, IEEE Transactions on Computers, v.48 n.10, p.1145-1152, October 1999
	M. H. Konijnenburg , J. Th. van der Linden , A. J. van de Goor, Illegal state space identification for sequential circuit test generation, Proceedings of the conference on Design, automation and test in Europe, p.146-es, January 1999, Munich, Germany
	Martin Keim , Nicole Drechsler , Rolf Drechsler , Bernd Becker, Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.17 n.1, p.37-51, February 2001
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Sequential Circuit Test Generation Using Dynamic State Traversal, Proceedings of the 1997 European conference on Design and Test, p.22, March 17-20, 1997
	A. Dargelas , C. Gauthron , Y. Bertrand, MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits, Proceedings of the 1997 European conference on Design and Test, p.29, March 17-20, 1997
	I. Pomeranz , S. M. Reddy, On improving genetic optimization based test generation, Proceedings of the 1997 European conference on Design and Test, p.506, March 17-20, 1997
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Alternating Strategies for Sequential Circuit ATPG, Proceedings of the 1996 European conference on Design and Test, p.368, March 11-14, 1996
	Franco Fummi , Marco Boschini , Xiaoming Yu , Elizabeth M. Rudnick, Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach, Journal of Electronic Testing: Theory and Applications, v.17 n.3-4, p.321-330, June-August 2001