On test set preservation of retimed circuits

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

On test set preservation of retimed circuits

Full text

Pdf (256 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 176 - 182

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Aiman El-Maleh	MACS Laboratory, McGill University, 3480 University St., Montreal, Canada, H3A 2A7
Thomas Marchok	ECE Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
Janusz Rajski	Mentor Graphics Corp., 8005 SW Boeckman Rd., Wilsonville, OR
Wojciech Maly	ECE Department, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/217474.217526 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. E1-Maleh, T.E. Marchok, J. Rajski, and W. Maly, "Behavior and testability preservation under the retiming transformation," McGill University Technical Report~94-R3, December, 1994, submitted to IEEE Trans. CAD.
	2	A. Ghosh, "Techniques for test generation and verification of VLSI sequential circuits," Ph.D. Dissertation, U.C. Berkeley Memorandum No. UCB/ERL M91/73, Sept. 1991.
	3	F. Hennie, Finite state models for logical machines, New York: John Wiley,1968.
	4	C.E. Leiserson and J.B. Saxe, "Optimizing synchronous systems," Journal of VLSI and Computer Systems, vol. 1, pp. 41-67, Spring 1983.
	5	C.E. Leiserson and J.B. Saxe, "Retiming synchronous circuitry," AIgorithmica, vol. 6, pp. 5-35, 1991.
	6	T.E. Marchok and W. Maly, "Automatic synthesis and the cost of testing," in Proc. Custom Integrated Circuit Conf., pp. 132-135, 1994.
	7	T.E. Marchok, A. E1-Maleh, W. Maly and J. Rajski, "Test set preservation under retiming transformation," presented at the First International Test Synthesis Worhshop, May 18-20, 1994, Santa Barbara, CA.
	8	T. E. Marchok , A. El-Maleh , W. Maly , J. Rajski, Complexity of sequential ATPG, Proceedings of the 1995 European conference on Design and Test, p.252, March 06-09, 1995
	9	Thomas M. Niermann , Wu-Tung Cheng , Janak H. Patel, Proofs: a fast, memory efficient sequential circuit fault simulator, Proceedings of the 27th ACM/IEEE conference on Design automation, p.535-540, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123396]
	10	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	11	C. Pixley and G. Beihl, "Calculating resetability and reset sequences," in Proc. ICCAD, pp. 376-379, December 1992.
	12	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	13	E. M. Sentovich et al., "SIS: a system for sequential circuit synthesis," U.C. Berkeley Memorandum No. UCB/ERL M92/41, May 1992.

CITED BY 8

	A. Ranjan , A. Srivastava , V. Karnam , M. Sarrafzadeh, Layout aware retiming, Proceedings of the 11th Great Lakes symposium on VLSI, p.25-30, March 2001, West Lafayette, Indiana, United States
	Soha Hassoun , Tiziano Villa, Optimization of synchronous circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen, Verifying sequential equivalence using ATPG techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.244-275, April 2001
	Boris Ratchev , Mike Hutton , Gregg Baeckler , Babette van Antwerpen, Verifying the correctness of FPGA logic synthesis algorithms, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Peichen Pan , C. L. Liu, Partial Scan with Preselected Scan Signals, IEEE Transactions on Computers, v.48 n.9, p.1000-1005, September 1999
	Thomas E. Marchok , Aiman El-Maleh , Janusz Rajski , Wojciech Maly, Testability Implications of Performance-Driven Logic Synthesis, IEEE Design & Test, v.12 n.2, p.32-39, June 1995
	Hiroyuki Yotsuyanagi , Seiji Kajihara , Kozo Kinoshita, Synthesis of Sequential Circuits by Redundancy Removal and Retiming, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.81-92, Aug. 1997
	Mahesh A. Iyer , David E. Long , Miron Abramovici, Surprises in Sequential Redundancy Identification, Proceedings of the 1996 European conference on Design and Test, p.88, March 11-14, 1996