A general method for compiling event-driven simulations

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A general method for compiling event-driven simulations

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 151 - 156

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Robert S. French	Computer Systems Laboratory, Stanford University, CA
Monica S. Lam	Computer Systems Laboratory, Stanford University, CA
Jeremy R. Levitt	Computer Systems Laboratory, Stanford University, CA
Kunle Olukotun	Computer Systems Laboratory, Stanford University, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 23, Citation Count: 14

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Z. Barzilai, J. L. Carter, B. K. Rosen, and J. D. Rutledge, "HSS - a high-speed simulator," IEEE Transactions on Computer-Aided Design, vol. 6, pp. 601-616, July 1987.
	2	Craig Hansen, Hardware logic simulation by compilation, Proceedings of the 25th ACM/IEEE conference on Design automation, p.712-716, June 12-15, 1988, Atlantic City, New Jersey, United States
	3	Emily J. Shriver , Karem A. Sakallah, Ravel: assigned-delay compiled-code logic simulation, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.364-368, November 1992, Santa Clara, California, United States
	4	Zhicheng Wang , Peter M. Maurer, LECSIM: a levelized event driven compiled logic simulation, Proceedings of the 27th ACM/IEEE conference on Design automation, p.491-496, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123349]
	5	D. M. Lewis, "A hierarchical compiled code event-driven logic simulator," IEEE Transactions on Computer-Aided Design, vol. 10, pp. 726-737, June 1991.
	6	Ernst Ulrich , Dennis Hebert, Speed and accuracy in digital network simulation based on structural modeling, Proceedings of the 19th conference on Design automation, p.587-593, January 1982
	7	Robert P. Wilson , Robert S. French , Christopher S. Wilson , Saman P. Amarasinghe , Jennifer M. Anderson , Steve W. K. Tjiang , Shih-Wei Liao , Chau-Wen Tseng , Mary W. Hall , Monica S. Lam , John L. Hennessy, SUIF: an infrastructure for research on parallelizing and optimizing compilers, ACM SIGPLAN Notices, v.29 n.12, p.31-37, Dec. 1994 [doi>10.1145/193209.193217]
	8	S. L. Coumeri and D. E. Thomas, "Benchmark descriptions for comparing the performance of Verilog and VHDL simulators," in Proceedings of the 1994 International Verilog HDL Conference, pp. 14-16, Mar. 1994.

CITED BY 14

	V. Krishnaswamy , P. Banerjee, Parallel compiled event driven VHDL simulation, Proceedings of the 12th international conference on Supercomputing, p.297-304, July 1998, Melbourne, Australia
	Charles J. DeVane, Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.154-161, November 09-13, 1997, San Jose, California, United States
	Adam Morawiec , Raimund Ubar , Jaan Raik, Cycle-based simulation algorithms for digital systems using high-level decision diagrams (poster paper), Proceedings of the conference on Design, automation and test in Europe, p.743, March 27-30, 2000, Paris, France
	Mark Stephenson , Jonathan Babb , Saman Amarasinghe, Bidwidth analysis with application to silicon compilation, ACM SIGPLAN Notices, v.35 n.5, p.108-120, May 2000
	Stephen A. Edwards, Tutorial: Compiling concurrent languages for sequential processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.141-187, April 2003
	Kunle Olukotun , Mark Heinrich , David Ofelt, Digital system simulation: methodologies and examples, Proceedings of the 35th annual conference on Design automation, p.658-663, June 15-19, 1998, San Francisco, California, United States
	Vasanth Asokan , Alexander G. Dean, Providing time- and space- efficient procedure calls for asynchronous software thread integration, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	V. Kirshnaswamy , G. Hasteer , P. Banerjee, Automatic Parallelization of Compiled Event Driven VHDL Simulation, IEEE Transactions on Computers, v.51 n.4, p.380-394, April 2002
	Benjamin J. Welch , Shobhit O. Kanaujia , Adarsh Seetharam , Deepaksrivats Thirumalai , Alexander G. Dean, Supporting Demanding Hard-Real-Time Systems with STI, IEEE Transactions on Computers, v.54 n.10, p.1188-1202, October 2005
	Nagendra J. Kumar , Siddhartha Shivshankar , Alexander G. Dean, Asynchronous software thread integration for efficient software, ACM SIGPLAN Notices, v.39 n.7, July 2004
	Dumitru Potop-Butucaru , Robert de Simone, Optimization for faster execution of Esterel programs, Formal methods and models for system design: a system level perspective, Kluwer Academic Publishers, Norwell, MA, 2004
	Stephen A. Edwards , Olivier Tardieu, Efficient code generation from SHIM models, ACM SIGPLAN Notices, v.41 n.7, July 2006
	Daniel Große , Rüdiger Ebendt , Rolf Drechsler, Improvements for constraint solving in the systemc verification library, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Nagendra J. Kumar , Vasanth Asokan , Siddhartha Shivshankar , Alexander G. Dean, Efficient software implementation of embedded communication protocol controllers using asynchronous software thread integration with time- and space-efficient procedure calls, ACM Transactions on Embedded Computing Systems (TECS), v.6 n.1, February 2007