Fast identification of robust dependent path delay faults

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Fast identification of robust dependent path delay faults

Full text

Pdf (295 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 119 - 125

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

U. Sparmann	Computer Science Dept., University of Saarland, D 66041 Saarbrücken, Germany
D. Luxenburger	Computer Science Dept., University of Saarland, D 66041 Saarbrücken, Germany
K.-T. Cheng	Department of ECE, University of California, Santa Barbara, CA
S. M. Reddy	Department of ECE, University of Iowa, Iowa City, IA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 10, Citation Count: 16

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/217474.217517 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	William K. Lam , Alexander Saldanha , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Delay fault coverage and performance tradeoffs, Proceedings of the 30th international conference on Design automation, p.446-452, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164970]
	2	Kwang-Ting Cheng , Hsi-Chuan Chen, Delay Testing for Non-Robust Untestable Circuits, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.954-961, October 17-21, 1993
	3	Z. Barzilai and B.K. Rosen. Comparision of AC self-testing procedures. In International Test Conference, pages 89-91, 1983.
	4	G.L. Smith. Model for delay faults based upon paths. In International Test Conference, pages 342-349, 1985.
	5	S.M. Reddy, C.J. Lin, and S. Patil. An automatic test pattern generator for the detection of path delay faults. In International Conference on CAD, pages 284-287, 1987.
	6	M. Schulz , F. Fink , K. Fuchs, Parallel pattern fault simulation of path delay faults, Proceedings of the 26th ACM/IEEE conference on Design automation, p.357-363, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74442]
	7	P.C. McGeer, A. Saldanha, P.R. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli. Timing analysis and delay fault test generation using path-recursive functions. In International Conference on CAD-91, pages 180-183, 1991.
	8	D. Bhattacharya , P. Agrawal , V. D. Agrawal, Delay fault test generation for scan/hold circuits using Boolean expressions, Proceedings of the 29th ACM/IEEE conference on Design automation, p.159-164, June 08-12, 1992, Anaheim, California, United States
	9	Irith Pomeranz , Sudhakar M. Reddy , Prasanti Uppaluri, NEST: A non-enumerative test generation method for path delay faults in combinational circuits, Proceedings of the 30th international conference on Design automation, p.439-445, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164967]
	10	Manfred Henftling , Hannes C. Wittmann , Kurt J. Antreich, Path hashing to accelerate delay fault simulation, Proceedings of the 31st annual conference on Design automation, p.522-526, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196523]
	11	Kwang-Ting Cheng , Hsi-Chuan Chen, Generation of high quality non-robust tests for path delay faults, Proceedings of the 31st annual conference on Design automation, p.365-369, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196423]
	12	K. Fuchs, M. Pabst, and T. RSssel. RESIST: A recursive test generation algorithm for path delay faults considering various test classes. IEEE Transactions on CAD, pages 1550-1562, 1994.
	13	F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In Proceedings IEEE International Symposium on Circuits and Systems, 1985.
	14	C.J. Lin and S.M. Reddy. On delay fault testing in logic circuits. IEEE Transactions on CAD, pages 694-703, September 1987.
	15	U. Sparmann, D. Luxenburger, K.T. Cheng, and S.M. Reddy. Fast identification of robust dependent path delay faults. Technical Report SFB 124 08/1994, Computer Science Department, Universit/~t des Saarlandes, D 66041 Saarbr/icken, Germany, 1994.
	16	I. Pomeranz and S.M. Reddy. An efficient non-enumerative method to estimate the path delay fault coverage in combinational circuits. IEEE Transactions on CAD, pages 240-250, 1994.
	17	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	18	Y.K. Malaiya and R. Narayanswamy. Testing for timing failures in synchronous sequential integrated circuits. In International Test Conference, pages 560-571, 1983.
	19	W.-N. Li, S.M. Reddy, and S.K. Sahni. On path selection in combinational logic circuits. IEEE Trans. on CAD, pages 56-63, 1989.

CITED BY 16

	Seiichiro Tani , Mitsuo Teramoto , Tomoo Fukazawa , Kazuyoshi Matsuhiro, Efficient Path Selection for Delay Testing Based on Path Clustering, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.75-85, August-October 1999
	A. Krstić , K. Cheng , S. Chakradhar, Testable path delay fault cover for sequential circuits, Proceedings of the conference on European design automation, p.220-226, September 1996, Geneva, Switzerland
	Mehrdad Nourani , Joan Carletta , Christos Papachristou, Integrated test of interacting controllers and datapaths, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.401-422, July 2001
	Amir Attarha , Mehradad Nourani , Carco Lucas, Modeling and simulation of real defects using fuzzy logic, Proceedings of the 37th conference on Design automation, p.631-636, June 05-09, 2000, Los Angeles, California, United States
	Wei-Cheng Lai , Angela Krstic , Kwang-Ting (Tim) Cheng, Functionally Testable Path Delay Faults on a Microprocessor, IEEE Design & Test, v.17 n.4, p.6-14, October 2000
	Andrzej Krasniewski, Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.4-6, p.283-296, September 2003
	Kwang-Ting Cheng , Angela Krstic , Hsi-Chuan Chen, Generation of High Quality Tests for Robustly Untestable Path Delay Faults, IEEE Transactions on Computers, v.45 n.12, p.1379-1392, December 1996
	Irith Pomeranz , Sudhakar M. Reddy, Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.679-689, October 2001
	Subhashis Majumder , Bhargab B. Bhattacharya , Vishwani D. Agrawal , Michael L. Bushnell, A new classification of path-delay fault testability in terms of stuck-at faults, Journal of Computer Science and Technology, v.19 n.6, p.955-964, November 2004
	Masayasu Fukunaga , Seiji Kajihara , Sadami Takeoka , Shinichi Yosimura, On effective criterion of path selection for delay testing, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Shun-Yen Lu , Pei-Ying Hsieh , Jing-Jia Liou, Exploring linear structures of critical path delay faults to reduce test efforts, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Angela Krstić , Kwang-Ting Cheng, Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.43-54, Aug. 1997
	Marwan A. Gharaybeh , Michael L. Bushnell , Vishwani D. Agrawal, Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.55-67, Aug. 1997
	Angela Krstic , Kwang-Ting Cheng, Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability, Proceedings of the 1996 European conference on Design and Test, p.486, March 11-14, 1996
	Bernd Becker , Rolf Drechsler , Rolf Krieger , Sudhakar M. Reddy, A Fast Optimal Robust Path Delay Fault Testable Adder, Proceedings of the 1996 European conference on Design and Test, p.491, March 11-14, 1996
	Ying-Yen Chen , Jing-Jia Liou, Diagnosis framework for locating failed segments of path delay faults, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.755-765, June 2008