Functional multiple-output decomposition

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Functional multiple-output decomposition: theory and an implicit algorithm

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 54 - 59

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Bernd Wurth	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Klaus Eckl	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Kurt Antreich	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 18

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	6	Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula, BDD based decomposition of logic functions with application to FPGA synthesis, Proceedings of the 30th international conference on Design automation, p.642-647, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165078]
	7	Y.-T. Lai, K.-R. R. Pan, M. Pedram, and S. Sastry, "FGMap: A Technology Mapping Algorithm for Look-Up Table Type FP- GAs Based on Function Graphs," Workshop Notes InternationaI Workshop on Logic Synthesis IWLS, pp. 961 -964, May 1993.
	8	Tsutomu Sasao, Logic Synthesis and Optimization, Kluwer Academic Publishers, Norwell, MA, 1997
	9	Rajeev Murgai , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Optimum functional decomposition using encoding, Proceedings of the 31st annual conference on Design automation, p.408-414, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196440]
	10	Y.-T. Lai, K.-R. R. Pan, and M. Pedram, "FPGA Synthesis using OBDD-based Function Decomposition," USC Technical Flep ort, 1994.
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	12	Y.-T. Lai, M. Pedram, and S. B. K. Vrudhula, "EVBDD-Based Algorithms for Integer Linear Programming, Spectral Transformation, and Function Decomposition," IEEE Transactions on Computer-Aided Design, vol. 13, no. 8, 1994.
	13	Olivier Coudert , Jean Christophe Madre , Henri Fraisse, A new viewpoint on two-level logic minimization, Proceedings of the 30th international conference on Design automation, p.625-630, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165071]
	14	Timothy Kam , Tiziano Villa , Robert Brayton , Alberto Sangiovanni-Vincentelli, A fully implicit algorithm for exact state minimization, Proceedings of the 31st annual conference on Design automation, p.684-690, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196615]
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CITED BY 18

	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Christian Legl , Bernd Wurth , Klaus Eckl, A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs, Proceedings of the 33rd annual conference on Design automation, p.730-733, June 03-07, 1996, Las Vegas, Nevada, United States
	Kenneth Yan, Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks, Proceedings of the 2001 conference on Asia South Pacific design automation, p.231-234, January 2001, Yokohama, Japan
	C. Scholl, Multi-output functional decomposition with exploitation of don't cares, Proceedings of the conference on Design, automation and test in Europe, p.743-748, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Victor N. Kravets , Karem A. Sakallah, Constructive library-aware synthesis using symmetries, Proceedings of the conference on Design, automation and test in Europe, p.208-215, March 27-30, 2000, Paris, France
	Jie-Hong R. Jiang , Jing-Yang Jou , Juinn-Dar Huang, Compatible class encoding in hyper-function decomposition for FPGA synthesis, Proceedings of the 35th annual conference on Design automation, p.712-717, June 15-19, 1998, San Francisco, California, United States
	Jason Cong , Yean-Yow Hwang, Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.27-34, February 22-25, 1998, Monterey, California, United States
	Jason Cong , Yean-Yow Hwang, Partially-dependent functional decomposition with applications in FPGA synthesis and mapping, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.35-42, February 09-11, 1997, Monterey, California, United States
	Jason Cong , Chang Wu, FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits, Proceedings of the 34th annual conference on Design automation, p.644-649, June 09-13, 1997, Anaheim, California, United States
	Jason Cong , Yean-Yow Hwang, Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.193-225, April 2000
	Jason Cong , Kenneth Yan, Synthesis for FPGAs with embedded memory blocks, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.75-82, February 10-11, 2000, Monterey, California, United States
	Jason Cong , Chang Wu , Yuzheng Ding, Cut ranking and pruning: enabling a general and efficient FPGA mapping solution, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.29-35, February 21-23, 1999, Monterey, California, United States
	Rolf Drechsler, Verifying integrity of decision diagrams, Integration, the VLSI Journal, v.32 n.1-3, p.61-75, November 2002
	Victor N. Kravets , Karem A. Sakallah, Resynthesis of multi-level circuits under tight constraints using symbolic optimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.687-693, November 10-14, 2002, San Jose, California
	Tsutomu Sasao , Munehiro Matsuura, A method to decompose multiple-output logic functions, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Chi-Chou Kao , Yen-Tai Lai, An efficient algorithm for finding the minimal-area FPGA technology mapping, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.168-186, January 2005
	C. Scholl , S. Melchior , G. Hotz , P. Molitor, Minimizing ROBDD Sizes of Incompletely Specified Boolean Functions by Exploiting Strong Symmetries, Proceedings of the 1997 European conference on Design and Test, p.229, March 17-20, 1997
	Christian Legl , Bernd Wurth , Klaus Eckl, An Implicit Algorithm for Support Minimization during Functional Decomposition, Proceedings of the 1996 European conference on Design and Test, p.412, March 11-14, 1996