Memory segmentation to exploit sleep mode operation

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Memory segmentation to exploit sleep mode operation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 36 - 41

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Amir H. Farrahi	Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL
Gustavo E. Téllez	Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL
Majid Sarrafzadeh	Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 48, Citation Count: 20

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	In International Workshop on Low Power Design, April 1994.
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	4	A. H. Farrahi, G. T~llez, and M. Sarrafzadeh. "Exploiting Sleep Mode Through Activity-Driven Partitioning". Technical report, Northwestern University, EECS Department, Evanston, IL, November 1994.
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	15	Y. C. Wet and C. K. Cheng. "Ratio-Cut Partitioning for Hierachical Designs". IEEE Transactions on Computer Aided Design, 40(7):911-99.1, July 1991.

CITED BY 20

	Gustavo E. Téllez , Amir Farrahi , Majid Sarrafzadeh, Activity-driven clock design for low power circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.62-65, November 05-09, 1995, San Jose, California, United States
	Luca Benini , Alberto Macii , Massimo Poncino, A recursive algorithm for low-power memory partitioning, Proceedings of the 2000 international symposium on Low power electronics and design, p.78-83, July 25-27, 2000, Rapallo, Italy
	Luca Benini , Luca Macchiarulo , Alberto Macii , Massimo Poncino, Layout-driven memory synthesis for embedded systems-on-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.96-105, April 2002
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Chi-Hong Hwang , Allen C.-H. Wu, A predictive system shutdown method for energy saving of event-driven computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.226-241, April 2000
	L. Benini , L. Macchiarulo , A. Macii , E. Macii , M. Poncino, From architecture to layout: partitioned memory synthesis for embedded systems-on-chip, Proceedings of the 38th conference on Design automation, p.784-789, June 2001, Las Vegas, Nevada, United States
	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	Luca Benini , Alberto Macii , Massimo Poncino, Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.1, p.5-32, February 2003
	Catherine H. Gebotys, Low energy memory and register allocation using network flow, Proceedings of the 34th annual conference on Design automation, p.435-440, June 09-13, 1997, Anaheim, California, United States
	Ki-Seok Chung , Taewhan Kim , C. I. Liu, Behavioral-level partitioning for low power design in control-dominated application, Proceedings of the 10th Great Lakes symposium on VLSI, p.156-161, March 02-04, 2000, Chicago, Illinois, United States
	Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha , Sujit Dey, Transforming control-flow intensive designs to facilitate power management, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.657-664, November 08-12, 1998, San Jose, California, United States
	Takanori Okuma , Yun Cao , Masanori Muroyama , Hiroto Yasuura, Reducing access energy of on-chip data memory considering active data bitwidth, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Michael J. Alexander, Power optimization for FPGA look-up tables, Proceedings of the 1997 international symposium on Physical design, p.156-162, April 14-16, 1997, Napa Valley, California, United States
	Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation, IEEE Design & Test, v.17 n.2, p.74-85, April 2000
	N. Julien , S. Gailhard , E. Martin, Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT, Journal of VLSI Signal Processing Systems, v.35 n.2, p.195-211, September 2003
	Russell Tessier , Vaughn Betz , David Neto , Thiagaraja Gopalsamy, Power-aware RAM mapping for FPGA embedded memory blocks, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000
	L. Benini , P. Vuillod , G. de Micheli , Claudionor Coelho, Synthesis of low-power selectively-clocked systems from high-level specification, Proceedings of the 9th international symposium on System synthesis, p.57, November 06-08, 1996
	Ozcan Ozturk , Mahmut Kandemir, Nonuniform Banking for Reducing Memory Energy Consumption, Proceedings of the conference on Design, Automation and Test in Europe, p.814-819, March 07-11, 2005
	Taemin Kim , Xun Liu, Better than optimum?: register reduction using idle pipelined functional units, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA