Register allocation and binding for low power

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Register allocation and binding for low power

Full text

Pdf (239 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 29 - 35

Year of Publication: 1995

ISBN:0-89791-725-1

Authors

Jui-Ming Chang	Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
Massoud Pedram	Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 54, Citation Count: 64

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/217474.217502 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Balakrishnan , P. Marwedel, Integrated scheduling and binding: a synthesis approach for design space exploration, Proceedings of the 26th ACM/IEEE conference on Design automation, p.68-74, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74395]
	2	J-M. Chang, M. Pedram,"Power Efficient Register Assignment", CENG Technical Report 95-03, University of Southern California, Mar. 1995.
	3	Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
	4	Jack Edmonds , Richard M. Karp, Theoretical Improvements in Algorithmic Efficiency for Network Flow Problems, Journal of the ACM (JACM), v.19 n.2, p.248-264, April 1972 [doi>10.1145/321694.321699]
	5	M.C.Golumbic, "Algorithmic Graph Theory and Perfect Graphs", Academic Press 1980.
	6	G. Goossens, D Lanneer, J. Vanhoof, J Rabaey, J. Van Meerbergen, and H. De Man. "Optimization-Based Synthesis of Multiprocessor Chips for Digital Signal Processing with Cathedral- II". In G. Saucier and P.M. McLellan, editor, Logic and Architecture Synthesis, 1988.
	7	Charles Y. Hitchcock, III , Donald E. Thomas, A method of automatic data path synthesis, Proceedings of the 20th conference on Design automation, p.484-489, June 27-29, 1983, Miami Beach, Florida, United States
	8	R. Hogg, A. Craig, "Introduction to Mathematical Statistics". fourth Edition. pp.147-152.
	9	David Ku , Gionvanni De Micheli, Relative scheduling under timing constraints, Proceedings of the 27th ACM/IEEE conference on Design automation, p.59-64, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123227]
	10	K. Kiiciikcakar and A. Parker. "MABAL, A Software Package for Module and Bus Allocation". International Journal of Computer Aided VLSI Design, pp. 419-436, 1990.
	11	F. J. Kurdahi , A. C. Parker, REAL: a program for REgister ALlocation, Proceedings of the 24th ACM/IEEE conference on Design automation, p.210-215, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37920]
	12	U. Lauther , Peter Duzy , Petra Michel, The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, Norwell, MA, 1992
	13	B.M. Pangrle and D.D Gaski, "Design Tools for Intelligent Silicon Compilation", IEEE trans, on CAD, 6(6), Nov. 1987.
	14	Christos H. Papadimitriou , Kenneth Steiglitz, Combinatorial optimization: algorithms and complexity, Prentice-Hall, Inc., Upper Saddle River, NJ, 1982
	15	A. Papoulis, "Probability, Random Variables, and Stochastic Processes". Third Edition, section 6.3, McGraw-Hill, 1991.
	16	P. G. Paulin , J. P. Knight, Scheduling and binding algorithms for high-level synthesis, Proceedings of the 26th ACM/IEEE conference on Design automation, p.1-6, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74383]
	17	L. Stok,"An Exact Polynomial Time Algorithm for Module Allocation", in Fifth International Workshop on High-Level Synthesis, Biihlerh6he, pp.69-76, March 3-9 1991.
	18	C.-J. Tseng and D.P. Siewiorek, "Automated Synthesis of Data Paths in Digital Systems", IEEE trans, on CAD, 5(3), July 1986.

CITED BY 64

	Yumin Zhang , Xiaobo (Sharon) Hu , Danny Z. Chen, Global register allocation for minimizing energy consumption, Proceedings of the 1999 international symposium on Low power electronics and design, p.100-102, August 16-17, 1999, San Diego, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Sumit Gupta , Nick Savoiu , Nikil Dutt , Rajesh Gupta , Alex Nicolau, Conditional speculation and its effects on performance and area for high-level snthesis, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Yumin Zhang , Xiaobo (Sharon) Hu , Danny Z. Chen, Efficient global register allocation for minimizing energy consumption, ACM SIGPLAN Notices, v.37 n.4, April 2002
	Mehrdad Nourani , Joan Carletta , Christos Papachristou, Synthesis-for-testability of controller-datapath pairs that use gated clocks, Proceedings of the 37th conference on Design automation, p.613-618, June 05-09, 2000, Los Angeles, California, United States
	Chi-Hong Hwang , Allen C.-H. Wu, A predictive system shutdown method for energy saving of event-driven computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.226-241, April 2000
	Neal K. Bambha , Shuvra S. Bhattacharyya , Jürgen Teich , Eckart Zitzler, Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors, Proceedings of the ninth international symposium on Hardware/software codesign, p.243-248, April 2001, Copenhagen, Denmark
	Chingren Lee , Jenq Kuen Lee , TingTing Hwang , Shi-Chun Tsai, Compiler optimization on instruction scheduling for low power, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Lars Kruse , Eike Schmidt , Gerd Jochens , Ansgar Stammermann , Wolfgang Nebel, Lower bound estimation for low power high-level synthesis, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States
	Neal K. Bambha , Shuvra S. Bhattacharyya, A joint power/performance optimization algorithm for multiprocessor systems using a period graph construct, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Sheayun Lee , Andreas Ermedahl , Sang Lyul Min, An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors, ACM SIGPLAN Notices, v.36 n.8, p.1-10, Aug. 2001
	Catherine H. Gebotys, Low energy memory and register allocation using network flow, Proceedings of the 34th annual conference on Design automation, p.435-440, June 09-13, 1997, Anaheim, California, United States
	Ki-Seok Chung , Taewhan Kim , C. I. Liu, Behavioral-level partitioning for low power design in control-dominated application, Proceedings of the 10th Great Lakes symposium on VLSI, p.156-161, March 02-04, 2000, Chicago, Illinois, United States
	Wen-Tsong Shiue, Retargetable compilation for low power, Proceedings of the ninth international symposium on Hardware/software codesign, p.254-259, April 2001, Copenhagen, Denmark
	Lars Kruse , Eike Schmidt , Gerd Jochens , Wolfgang Nebel, Lower and upper bounds on the switching activity in scheduled data flow graphs, Proceedings of the 1999 international symposium on Low power electronics and design, p.115-120, August 16-17, 1999, San Diego, California, United States
	M. Pedram , J. Chang, Module assignment for low power, Proceedings of the conference on European design automation, p.376-381, September 1996, Geneva, Switzerland
	Nikolaos Bellas Ibrahim Hajj , George Stamoulis , N. Bellas , C. Polychronopoulos, Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors, Proceedings of the 1998 international symposium on Low power electronics and design, p.70-75, August 10-12, 1998, Monterey, California, United States
	Catherine H. Gebotys, A network flow approach to memory bandwidth utilization in embedded DSP core processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.390-398, August 2002
	Sungpack Hong , Taewhan Kim, Bus optimization for low-power data path synthesis based on network flow method, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Chun Gi Lyuh , Taewhan Kim , C. L. Liu, An integrated data path optimization for low power based on network flow method, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Azadeh Davoodi , Ankur Srivastava, Effective graph theoretic techniques for the generalized low power binding problem, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Chingren Lee , Jenq Kuen Lee , Tingting Hwang , Shi-Chun Tsai, Compiler optimization on VLIW instruction scheduling for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.252-268, April 2003
	Chun-Gi Lyuh , Taewhan Kim , Ki-Wook Kim, Coupling-aware high-level interconnect synthesis for low power, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.609-613, November 10-14, 2002, San Jose, California
	W. Wang , T. K. Tan , J. Luo , Y. Fei , L. Shang , K. S. Vallerio , L. Zhong , A. Raghunathan , N. K. Jha, A comprehensive high-level synthesis system for control-flow intensive behaviors, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Yann-Rue Lin , Cheng-Tsung Hwang , Allen C.-H. Wu, Scheduling techniques for variable voltage low power designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.81-97, April 1997
	Ankur Srivastava , Majid Sarrafzadeh, Predictability: definition, ananlysis and optimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.118-121, November 10-14, 2002, San Jose, California
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, High-level macro-modeling and estimation techniques for switching activity and power consumption, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.538-557, August 2003
	Azadeh Davoodi , Vishal Khandelwal , Ankur Srivastava, High level techniques for power-grid noise immunity, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Eren Kursun , Ankur Srivastava , Seda Ogrenci Memik , Majid Sarrafzadeh, Early evaluation techniques for low power binding, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Jumpei Uchida , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki, A thread partitioning algorithm in low power high-level synthesis, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.74-79, January 27-30, 2004, Yokohama, Japan
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Temperature-aware resource allocation and binding in high-level synthesis, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Peak temperature control and leakage reduction during binding in high level synthesis, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Yi-Ping You , Chung-Wen Huang , Jenq Kuen Lee, A sink-n-hoist framework for leakage power reduction, Proceedings of the 5th ACM international conference on Embedded software, September 18-22, 2005, Jersey City, NJ, USA
	Deming Chen , Jason Cong , Junjuan Xu, Optimal module and voltage assignment for low-power, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yi-Ping You , Chingren Lee , Jenq Kuen Lee, Compilers for leakage power reduction, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.1, p.147-164, January 2006
	Azadeh Davoodi , Ankur Srivastava, Effective techniques for the generalized low-power binding problem, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.1, p.52-69, January 2006
	Zili Shao , Bin Xiao , Chun Xue , Qingfeng Zhuge , Edwin H.-M. Sha, Loop scheduling with timing and switching-activity minimization for VLIW DSP, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.1, p.165-185, January 2006
	Azadeh Davoodi , Ankur Srivastava, Simultaneous floorplanning and resource binding: a probabilistic approach, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Azadeh Davoodi , Ankur Srivastava, Voltage scheduling under unpredictabilities: a risk management paradigm, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.354-368, April 2005
	Chun-Gi Lyuh , Taewhan Kim, High-level synthesis for low power based on network flow method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.364-375, June 2003
	Lin Zhong , Niraj K. Jha, Interconnect-aware high-level synthesis for low power, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.110-117, November 10-14, 2002, San Jose, California
	Zili Shao , Qingfeng Zhuge , Meilin Liu , Chun Xue , Edwin H. M. Sha , Bin Xiao, Algorithms and analysis of scheduling for loops with minimum switching, International Journal of Computational Science and Engineering, v.2 n.1/2, p.88-97, June 2006
	Deming Chen , Jason Cong , Yiping Fan , Junjuan Xu, Optimality study of resource binding with multi-Vdds, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Pilok Lim , Taewhan Kim, Thermal-aware high-level synthesis based on network flow method, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Deming Chen , Jason Cong , Junjuan Xu, Optimal simultaneous module and multivoltage assignment for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.362-386, April 2006
	Jason Cong , Yiping Fan , Wei Jiang, Platform-based resource binding using a distributed register-file microarchitecture, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Min Ni , Seda Ogrenci Memik, Thermal-induced leakage power optimization by redundant resource allocation, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Gerd Jochens , Lars Kruse , Eike Schmidt , Wolfgang Nebel, A new parameterizable power macro-model for datapath components, Proceedings of the conference on Design, automation and test in Europe, p.8-es, January 1999, Munich, Germany
	A. Stammermann , D. Helms , M. Schulte , A. Schulz , W. Nebel, Binding, Allocation and Floorplanning in Low Power High-Level Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.544, November 09-13, 2003
	Ankur Srivastava , Seda Ogrenci Memik , Bo-Kyung Choi , Majid Sarrafzadeh, Achieving Design Closure Through Delay Relaxation Parameter, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.54, November 09-13, 2003
	J. E. Crenshaw , M. Sarrafzadeh, Accurate high level datapath power estimation, Proceedings of the 1997 European conference on Design and Test, p.590, March 17-20, 1997
	Cheng-Tao Hsieh , Jason Cong , Zhiru Zhang , Shih-Chieh Chang, Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	L. Benini , P. Vuillod , G. de Micheli , Claudionor Coelho, Synthesis of low-power selectively-clocked systems from high-level specification, Proceedings of the 9th international symposium on System synthesis, p.57, November 06-08, 1996
	Pushkar Tripathi , Rohan Jain , Srikanth Kurra , Preeti Ranjan Panda, REWIRED: REgister Write Inhibition by REsource Dedication, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Yi-Ping You , Chung-Wen Huang , Jenq Kuen Lee, Compilation for compact power-gating controls, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.4, p.51-es, September 2007
	Min Ni , Seda Ogrenci Memik, Early planning for clock skew scheduling during register binding, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Zili Shao , Qingfeng Zhuge , Youtao Zhang , Edwin H-M. Sha, Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors, International Journal of High Performance Computing and Networking, v.1 n.1-3, p.4-16, August 2004
	Jason Cong , Junjuan Xu, Simultaneous FU and register binding based on network flow method, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Rajarshi Mukherjee , Seda Ogrenci Memik, An integrated approach to thermal management in high-level synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.11, p.1165-1174, November 2006
	Junbo Yu , Qiang Zhou , Jinian Bian, Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Jason Cong , Yiping Fan , Junjuan Xu, Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.14 n.3, p.1-31, May 2009
	Meikang Qiu , Meiqin Liu , Hao Li , Hung-Chung Huang , Wenyuan Li , Jiande Wu, Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture, Journal of Signal Processing Systems, v.57 n.3, p.363-379, December 2009