aItPm: a strategy for integrating IP with ATM

ABSTRACT

This paper describes research on new methods and architectures that enable the synergistic combination of IP and ATM technologies. We have designed a highly scalable gigabit IP router based on an ATM core and a set of tightly coupled general-purpose processors. This a^It^Pm (pronounced "IP on ATM" or, if you prefer, "ip-attem") architecture provides flexibility in congestion control, routing, resource management, and packet scheduling.The a^It^Pm architecture is designed to allow experimentation with, and fine tuning of, the protocols and algorithms that are expected to form the core of the next generation IP in the context of a gigabit environment. The underlying multi-CPU embedded system will ensure that there are enough CPU and memory cycles to perform all IP packet processing at gigabit rates. We believe that the a^It^Pm architecture will not only lead to a scalable high-performance gigabit IP router technology, but will also demonstrate that IP and ATM technologies can be mutually supportive.

REFERENCES

• 1: Asthana, A., C. Delph, H. Jagadish, and P. Krzyzanowski "Towards a Gigabit IP Router", Journal of High Speed Networks, Vol. i, No. 4, pp. 281-288, 1992.
• 2: ATM Forum, "UTOPIA, An ATM.PHY Interface Specification,'' Level 1, Version 2.01, March 21, 1994
• 3: David D. Clark , Scott Shenker , Lixia Zhang, Supporting real-time applications in an Integrated Services Packet Network: architecture and mechanism, Conference proceedings on Communications architectures & protocols, p.14-26, August 17-20, 1992, Baltimore, Maryland, United States
• 4: Z. D. Dittia , J. R. ,. Cox Jr , G. M. Parulkar, Design of the APIC: A high performance ATM host-network interface chip, Proceedings of the Fourteenth Annual Joint Conference of the IEEE Computer and Communication Societies (Vol. 1)-Volume, p.179, April 02-06, 1995
• 5: Dittia, Zubin, Jerome R. Cox, Jr. and Guru Parulkar. "Catching Up With the Networks: Host I/O at Gigabit Rates," Technical Report WUCS-94-11, Department of Computer Science, Washington University in St. Louis, 1994.
• 6: Dittia, Zubin, Jerome R. Cox, Jr. and Guru Parulkar. "Using an ATM Interconnect as a High Performance i/O Backplane," Proceedings of the Hot Interconnects Symposium, August 1994.
• 7: Dittia, Zubin, Andy Fingerhut and Jonathan Tumer. "A Gigabit Local ATM Testbed for Multimedia Applications: System Architecture Document for Gigabit Switching Technology," Applied Research Lab, Working Note 94-11.
• 8: Ferrari, D. and D. Verma. A Scheme for Real-Time Channel Establishment in Wide-Area Networks, In iEEE JSA C, Vol. 8, No. 4, pp 368-379, April 1990.
• 9: Floyd, Sally, "Talk given at Maryland High Speed Workshop," March, 1992
• 10: S. J. Golestani, A stop-and-go queueing framework for congestion management, Proceedings of the ACM symposium on Communications architectures & protocols, p.8-18, September 26-28, 1990, Philadelphia, Pennsylvania, United States
• 11: Golestani, S. J. Duration-Limi'.- o : ~stical Multiplexing of Delay Sensitive Traffic in Pac,'L's, In Proceedings of INFOCOM '91, 1991.
• 12: Jay Hyman , Aurel A. Lazar , Giovanni Pacifici, MARS: the magnet II real-time scheduling algorithm, Proceedings of the conference on Communications architecture & protocols, p.285-293, September 03-06, 1991, Zurich, Switzerland
• 13: Hyman, J., A. Lazar, and G. Pacii. Real-Time Scheduling with Quality of Service Constrabi , In IEEE JSAC, Vol. 9, No. 9, pp 1052-1063, September 11.
• 14: Kalmanek, C.,, H. Kanakia, and Keshav. Rate Controlled Servers for Very High-Speed Net rks, In Proceedings of GlobeCom '90, pp 300.3.1-300.35.1990.
• 15: NetStar, Inc. GigaRouter Systerf,escription. Publication SPD000001, July 1994, Revision 7.
• 16: Craig Partridge, Gigabit networking, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1994
• 17: Gurudatta M. Parulkar, The next generation of internetworking, ACM SIGCOMM Computer Communication Review, v.20 n.1, p.18-43, Jan. 1990 [doi>10.1145/86587.86588]
• 18: "SPARC MBUS Interface Specificati Revision 1.2", SPARC international, April 1991.
• 19: Tumer, Jonathan S. "Progress Toward Optimal Nonblocking Multipoint Virtual Circuit Switching Networks," Proceedings of the Thirty-First Annual Allerton Conference on Communication, Control, and Computing, September 1993, pp. 760- 769.
• 20: Turner, Jonathan S. "An Optimal Nonblocking Multicast Virtual Circuit Switch," Proceedings oflnfocom, June 1994, pp. 298-305.
• 21: Tantawy, Ahmed, Odysseas Koufopavlou,Martina Zitterbart and Joseph Abler. "On the Design of a Multigigabit IP Router," Journal of High Speed Networks, vol. 3, no. 3, 1994.
• 22: Verma, D., H. Zhang, and D. Ferrari. Delay Jitter Control for Real-Time Communication in a Packet Switching Network, In Proceedings of TriCom '91, pp 35-43, 1991.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.2 Network Protocols

          Nouns: TCP/IP

Additional Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.1 Network Architecture and Design

          Nouns: Internet

General Terms:
Algorithms, Design, Performance