The design of RPM: an FPGA-based multiprocessor emulator

ABSTRACT

Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, greatly simplify the design of large circuits. The RPM (Rapid Prototype Engine for Multiprocessors) Project leverages these two technological advances. Its goal is to develop a common hardware platform for the emulation of multiprocessor systems with different architectures.For cost reasons, the use of FPGAs in RPM is limited to the memory controllers, while the rest of the emulator, including the processors, memories and interconnect, is built with off-the-shelf components. A flexible non-intrusive event logging mechanism is included at all levels of the memory hierarchy, making it possible to monitor the emulation in very fine detail. This paper presents the hardware design of RPM.

REFERENCES

• 1: Aptix Inc., Data Book, Aptix, San Jose, 1993.
• 2: Luiz André Barroso , Sasan Iman , Jaeheon Jeong , Koray Öner , Michel Dubois , Krishnan Ramamurthy, RPM: A Rapid Prototyping Engine for Multiprocessor Systems, Computer, v.28 n.2, p.26-34, February 1995 [doi>10.1109/2.347997]
• 3: Ben Catanzaro, Multiprocessor system architectures, Prentice-Hall, Inc., Upper Saddle River, NJ, 1994
• 4: Jaswinder P Singh , Wolf Weber , Anoop Gupta, SPLASH: Stanford parallel applications for shared-memory, Stanford University, Stanford, CA, 1991
• 5: Michel, Dubois , Christoph Scheurich , Fayé A. Briggs, Synchronization, Coherence, and Event Ordering in Multiprocessors, Computer, v.21 n.2, p.9-21, February 1988 [doi>10.1109/2.15]
• 6: Erik Hagersten , Anders Landin , Seif Haridi, DDM: A Cache-Only Memory Architecture, Computer, v.25 n.9, p.44-54, September 1992 [doi>10.1109/2.156381]
• 7: INCA, "VA-II Logic Emulator", INCA, Berkshire, United Kingdom, 1993.
• 8: Ko, B. and Maholtra, L., "Logic Emulation for System- Level Design", Prec. Electro, 1992.
• 9: Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Wolf-Dietrich Weber , Anoop Gupta , John Hennessy , Mark Horowitz , Monica S. Lam, The Stanford Dash Multiprocessor, Computer, v.25 n.3, p.63-79, March 1992 [doi>10.1109/2.121510]
• 10: Kai Li , Paul Hudak, Memory coherence in shared virtual memory systems, ACM Transactions on Computer Systems (TOCS), v.7 n.4, p.321-359, Nov. 1989 [doi>10.1145/75104.75105]
• 11: Maliniak, L., "Logic Emulation Meets the Demands of CPU Designers", Electronic Design, vol. 41, no. 7, pp. 36- 40, 1993.
• 12: Per Stenström, A Survey of Cache Coherence Schemes for Multiprocessors, Computer, v.23 n.6, p.12-24, June 1990 [doi>10.1109/2.55497]
• 13: Trimberger, S.,"A Reprogrammable Gate Array and Applications," Proceedings of the IEEE, Vol. 81, No. 7, pp. 1030-1041, July 1993.
• 14: Walters, S., "Reprogrammable Hardware Emulation Automates System Level ASIC Validation," Prec. WESCON, 199011

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids

          Nouns: VHDL

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Multiple-instruction-stream, multiple-data-stream processors (MIMD)

General Terms:
Design, Languages

Keywords:
field-programmable gate arrays, logic emulation, message-passing multicomputers, rapid prototyping, shared-memory multiprocessors