Hardware/software partitioning and minimizing memory interface traffic

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Hardware/software partitioning and minimizing memory interface traffic

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European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Grenoble, France

Pages: 226 - 231

Year of Publication: 1994

ISBN:0-89791-685-9

Authors

Axel Jantsch	Electronic System Design Laboratory, Royal Institute of Technology, ESDLab, Electrum 229, S-16440 Kista, Sweden
Peeter Ellervee	Electronic System Design Laboratory, Royal Institute of Technology, ESDLab, Electrum 229, S-16440 Kista, Sweden
Ahmed Hemani	Electronic System Design Laboratory, Royal Institute of Technology, ESDLab, Electrum 229, S-16440 Kista, Sweden
Johnny Öberg	Electronic System Design Laboratory, Royal Institute of Technology, ESDLab, Electrum 229, S-16440 Kista, Sweden
Hannu Tenhunen	Electronic System Design Laboratory, Royal Institute of Technology, ESDLab, Electrum 229, S-16440 Kista, Sweden

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 18, Citation Count: 14

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Peter Mark Athanas, An adaptive machine architecture and compiler for dynamic processor reconfigurations, Brown University, Providence, RI, 1992
	2	Th. Benne-r, J. Henkel, and R. Ernst, "Internal representation of Embedded HW/SW Systems", 2nd IFIP International Workshop on HW-SW Codesign, May 1993.
	3	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	4	Martin Edwards, "A Development System for Hardware/ Software Co-Synthesis using FPGAs", Second IFIP International Workshop on HW-SW CoDesign, May 1993.
	5	Peeter Ellervee, Axel Jantsch, Johnny aberg. and Ahmed Hemani, "Nestimator - A Neural Network Based Estimator", accepted for publication at 7th Annual IEEE International ASIC Conference, ASIC'94. September 1994.
	6	R. Ernst and J. Henkel. "Hardware-Software Codesign of Embedded Controllers Based on Hardware extraction", Inf. Workshop on HW-SW Codesign. September 1992.
	7	Rajesh K. Gupta and Giovanni De Micheli, "System-level Synthesis using Re-programmable Components", Proceedings of the European Design Automation Conference, 1992.
	8	Shousheng He and Mats Torkelson, "FPGA Application in an SBbus Based Rapid Prototyping System for ASDP", ICCD 1991.
	9	Ahmed Hemani , Adam Postula, A neural net based self organising scheduling algorithm, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	10	Axe1 Jantsch, Peeter Ellervee, Johnny oberg, Ahmed Hemani, and Hannu Tenhunen, "A Software Oriented Approach to Hardware/Software Codesign", Proceedings of the Poster Session of Ihe International Conference on Compiler Consfrucbon, Edinburgh, April 1994.
	11	Axel Jantsch, Peeter Ellervee, Johnny &erg, Ahmed Hemani, and Hannu Tenhunen, "A Case Study on Hardware/ Software Partitioning', Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1994.
	12	Richard M. Stallman, Using and Porting GNU CC, Free Software Foundation, Decemberl992, version 2.3.
	13	J. Varghese, M. Butts, and J. Batcheller, "An efficient logic emulation system", IEEE Trans. VLSI Systems, vol. 1, no. 2, pp. 171 - 174. June 1993.

CITED BY 14

	Jan Madsen , Bjarne Hald, An approach to interface synthesis, Proceedings of the 8th international symposium on System synthesis, p.16-21, September 13-15, 1995, Cannes, France
	James Smith , Giovanni De Micheli, Automated composition of hardware components, Proceedings of the 35th annual conference on Design automation, p.14-19, June 15-19, 1998, San Francisco, California, United States
	Jörg Henkel , Rolf Ernst, A path-based technique for estimating hardware runtime in HW/SW-cosynthesis, Proceedings of the 8th international symposium on System synthesis, p.116-121, September 13-15, 1995, Cannes, France
	Jörg Henkel , Rolf Ernst, A path-based technique for estimating hardware runtime in HW/SW-Cosynthesis, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Julio Leao da Silva, Jr. , Chantal Ykman-Couvreur , Miguel Miranda , Kris Croes , Sven Wuytack , Gjalt de Jong , Francky Catthoor , Diederik Verkest , Paul Six , Hugo De Man, Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer, Proceedings of the 35th annual conference on Design automation, p.76-81, June 15-19, 1998, San Francisco, California, United States
	Jörg Henkel , Rolf Ernst, A hardware/software partitioner using a dynamically determined granularity, Proceedings of the 34th annual conference on Design automation, p.691-696, June 09-13, 1997, Anaheim, California, United States
	Bharat P. Dave , Niraj K. Jha, COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems for Low Overhead Fault Tolerance, IEEE Transactions on Computers, v.48 n.4, p.417-441, April 1999
	Zoltán Ádám Mann , András Orbán , Péter Arató, Finding optimal hardware/software partitions, Formal Methods in System Design, v.31 n.3, p.241-263, December 2007
	Jui-Ming Chang , Massoud Pedram, Codex-dp: co-design of communicating systems using dynamic programming, Proceedings of the conference on Design, automation and test in Europe, p.114-es, January 1999, Munich, Germany
	M. Sanchez-Elez , M. Fernandez , M. Anido , H. Du , N. Bagherzadeh , R. Hermida, Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.10036, March 03-07, 2003
	Joerg Henkel , Rolf Ernst, The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.52, March 18-20, 1996
	Peter Voigt Knudsen , Jan Madsen, PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.85, March 18-20, 1996
	Martyn Edwards, Software acceleration using programmable logic: is it worth the effort?, Proceedings of the 5th International Workshop on Hardware/Software Co-Design, p.135, March 24-26, 1997
	Ch. Ykman-Couvreur , J. Lambrecht , D. Verkest , F. Catthoor , H. de Man, Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications, Proceedings of the 12th international symposium on System synthesis, p.85, November 01-04, 1999